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PMC-Sierra 64-bit processors consume 2.5W

Posted: 22 May 2002 ?? ?Print Version ?Bookmark and Share

Keywords:rm7000c? rm7065c? rm7000? rm7000a? rm7000b?

PMC-Sierra Inc. has introduced the RM7000C and RM7065C 64-bit MIPS-based processors that consume 2.5W at 600MHz, and are suitable for use in network router control planes, enterprise switches, networked printers, and STBs.

The RM7000C delivers a maximum production clock rate of 600 MHz and is also available at a rate of 533 MHz. It provides a pin-compatible speed upgrade for the company's RM7000, RM7000A, RM7000B, and RM5271 products.

It also features an external cache controller for up to 64MB of L3 cache that can be directly accessed to increase application performance. The company claims that the EZ cache mode operation reduces system cost and complexity by enabling the RM7000C to quickly access the off-chip L3 cache without the need for Tag RAMs.

The RM7065C does not include the L3 cache controller functionality.

Manufactured using a 0.13?m, copper-interconnect technology process, both fourth-generation processors are equipped with 256KB of integrated Level 2 cache, as well as 16KB each for the independent Level 1 instruction and data caches.

An enhanced system interface on both processors provide compatibility with legacy system controllers (LVTTL levels: 2.5V or 3.3V) to increase speeds up to 133MHz, as well as next generation controllers (HSTL level: 1.5V) for speeds up to 200MHz.

The RMC7000C is shipped in a 304-pin TBGA package and is priced starting at $106 (533MHz) for 10,000-unit quantities. The RM7065C is available in a 256-pin TBGA package and is quoted at $81 (533MHz).

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