3.3V series added to lines of ISP CPLDs
Keywords:ispmach 4000? ispmach 4000b? ispmach4000c? in system programmable cpld? complex programmable logic device?
The company now offers all three series in a single architecture, in 32, 64, 128, 256, 384 and 512-macrocell densities, and in I/O counts from 30 to 208. The 3.3V series can hit 380MHz with 2.5ns tPD (pin-to-pin logic delay) and low dynamic power consumption.
The devices provide logic implementation for many glue logic, state machine, decoder, bridging, power-up and signal handshaking functions, all of which are critical for implementing high-performance computing, communications, and industrial applications.
Designers of high-performance computing and communications systems, which traditionally have had relatively unlimited power budgets, are increasingly interested in lowering power consumption to reduce operating costs and power dissipation challenges, and enhance system reliability.
Replacing sense amplifiers with CMOS equivalents and using low-power, nonvolatile cells result in allowed static current as low as 1mA.
A 1.8V core helps reduce dynamic power consumption, and the company estimated that its ispMACH 4256C device typically dissipates 78 percent less power at 100MHz than other commercially available 1.8V or 2.5V CPLD solution.
The ispMACH 4000 devices have a pair of I/O banks, each with its own power-supply voltage that can be set at the appropriate voltage to support LVTTL and LVCMOS 3.3V, 2.5V and 1.8V outputs.
Device input buffers have programmable thresholds that support defined standards independent of the I/O bank voltage. All of the devices in the ispMACH 4000V/B/C families are available now.
Packages offered include 44-TQFP, 48-TQFP, 100-TQFP, 128-TQFP, 176-TQFP, and 256-ball fpBGA. For high-volume applications, pricing for the 1.8V ispMACH 4032CB and ispMACH 4256C is projected to be <$1. The ispMACH 4512C will be priced below $15.
EE Times |
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