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TSMC adopts Cadence's signal analysis for reference design flow

Posted: 30 May 2002 ?? ?Print Version ?Bookmark and Share

Keywords:CeltIC? signal-integrity analysis solution? reference design flow? CMOS IC?

Taiwan Semiconductor Mfg Co. (TSMC) has adopted Cadence Design System Inc.'s CeltIC signal-integrity analysis solution for its 0.135m reference design flow.

CeltIC is a crosstalk analyzer for digital CMOS ICs that calculates the impact of crosstalk on both functionality and delay. It analyzes and propagates glitch noise to verify noise immunity and ensure functional validity of the circuit. It also outputs noise induced delay changes in SDF format for feedback to static timing analysis. Additionally, CeltIC repairs crosstalk problems and generate ECOs for place-and-route.

"TSMC has successfully used CeltIC to check for coupling noise problems on a number of design tapeouts," said Genda Hu, VP of marketing at TSMC. "CeltIC has become an integral component of our deep-submicron design flow," Hu expressed.

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