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Optical-to-electrical conversion for long-haul networks

Posted: 01 Jun 2002 ?? ?Print Version ?Bookmark and Share

Keywords:optoelectronics? optocoupler? dwdm? cmos? fec?

While the need for electronic components in access networks, LANs or storage area networks (SANs) is obvious, the case for metro and long-haul networks requires closer examination. In the last two years, there have been many attempts to transfer the core of the broadband network entirely to optical. Even so, optical-to-electronic conversion is required in core optical networks and will still be required for years to come despite the impressive advances in the photonic industry.

O-E-O conversion

How is the optical-electrical-optical conversion done? For regeneration applications, the optical signal is received by a photodiode (PD), whose resulting small output electrical current is converted to a voltage-domain signal by a transimpedance amplifier (TIA) and sent to a clock recovery and synthesis unit (CRSU). The CRSU recovers the clock information from the data stream using PLL or digital phase-picker circuitry, demultiplexes the signal down to lower speeds and sends it to a forward error correction (FEC) device. While at lower data rates FEC functionality is optional, it becomes a necessity at OC-192 rates and above due to the significant optical signal degradation caused by polarization-mode and chromatic mode dispersions.

After correcting for transmission errors, the FEC chip sends the electrical signal to a second CRSU device. Now in the transmit direction, the second CRSU transceiver synthesizes a clock from a given reference and uses it to re-time and multiplex the transmitted data. The data is then sent to the laser driver (LD), which modulates the laser. For network flexibility, the ideal laser should be a tunable device that can generate optical signals in a certain optical bandwidth, not just one particular wavelength.

The laser, laser driver, photodiode and transimpedance amplifier together creates an optical data link (ODL) module. The CRSU mux/demux may be part of the ODL module or it may be placed on the PCB board. Both variants are available commercially. If the CRSU has difficulty resolving the very small signals received from the TIA, then an extra component, such as a limiting amplifier or post-amplifier, may be required. And an external laser modulator is required to handle HFs.

Design challenges

What are the complexities and challenges of building the existing electronic devices in O-E-O converters? Transimpedance amplifiers are the most sensitive to noise. As a result, they have traditionally resisted chip integration and are frequently manufactured in exotic bipolar technologies. Many attempts to design TIAs in CMOS have been made recently but the performance of the finished devices is still poor. Presently, the TIA is often integrated with an avalanche photodiode.

From a high-speed analog design perspective, the CRSU transceiver is the most demanding device to build. Despite the threat of directly sending IP traffic over DWDM, today's networks are still SONET/SDH based and likely will remain so for a while due to ILEC dominance. Therefore, the transceiver needs to be compliant with the rigorous Bellcore SONET/SDH jitter specification. In particular, achieving a 0.1UIp-p (Unit Interval peak-to-peak) of intrinsic jitter while transmitting the SONET/SDH data stream imposes harsh requirements on the phase noise characteristics of the synthesizer's PLL. It takes years of analog design experience to build manufacturable and jitter-compliant devices.

The FEC device is the most demanding device to build from the algorithmic point of view. The key here is to deliver the highest coding gain with the lowest overhead rate.

Manufacturing processes

In the first generation core network, deployment devices were typically manufactured in an exotic process like GaAs or SiGe. Since neither GaAs nor SiGe offers integration possibilities and both processes have lower yields than CMOS, they are typically displaced in a second-generation deployment by CMOS parts. Presently, 0.13m CMOS processing power is sufficient to design and manufacture OC-192 SONET/SDH compliant transceivers that consume half the power of their SiGe counterparts.

Going forward to OC-768 rates, this deployment scenario likely will not change. In the race to 40Gbps performance, however, Indium Phosphide (InP) currently seems to be the leader, as the raw speed power of this technology is the highest, with SiGe technology trying to catch-up. In the meantime, the photonic industry is working to improve the performance of its components so they can work directly with CMOS-based CRSU devices without need for TIAs.

Another trend in the manufacturing process is device miniaturization through integration of a photonic device, like a photodiode receiver, with an electronic device, like the CRSU transceiver. If both components are manufactured in InP, this integration is possible, even today. However, the problem is that photonic devices require very careful alignment to the fiber resulting in a high cost of packaging and assembly.

However, the inherent functional shortcomings of optical devices make it unlikely that the core of the network will become entirely optical. Most importantly, the lack of an effective method of wavelength conversion or re-mapping, coupled with the economies of scale and ever increasing performance of the technology mean that electronic devices will continue to be deployed at 10Gbps and 40Gbps rates. Even as future networks rates increase, the need for this optical-to-electrical conversion will likely continue to address functions that are not feasible optically.

? Krzysztof Iniewski

Manager of Strategic Marketing

Optical Networking Division

PMC-Sierra





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