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Public division belies private cooperation of PCI rivals

Posted: 05 Jun 2002 ?? ?Print Version ?Bookmark and Share

Keywords:PCI bus? PCI Developers Conference? Intel? IBM? PCI Express?

The split between developers over the future of the PCI bus was readily apparent in contrasting keynotes by representatives from Intel Corp. and IBM Corp. at the PCI Developers Conference last Monday (June 3). But behind the scenes, engineering teams from the conflicting PCI Express and PCI X 2.0 camps have started to hammer out a path to interoperabilty between the two approaches.

Intel's Louis Burns, co-general manager of the company's desktop products group, used his keynote to rally the several hundred engineers here to get in step with the rollout starting late next year of the serial PCI Express spec across all systems. And in his keynote, IBM's Steven Hetzler exhorted attendees to adopt PCI X 2.0, an extension of the parallel PCI bus using double-data-rate and quad-data-rate signaling, as a more stepwise evolution with a long-term future for servers.

Intel will sample chip sets using the 2.5Gbps PCI Express technology in the third quarter of 2003. The company is also promoting a highly compact desktop concept dubbed Tidewater which will use PCI Express to pack powerful processors and peripherals into a form factor that can be plugged in like a videotape cartridge.

"Our intent is to ship volume products [using PCI Express in desktops] in early 2004," said keynoter Burns. "We are doing a lot of [PCI Express] silicon development not only in the desktop space, but in servers and communications."

Intel and at least one other chip maker already have versions of PCI Express running in the labs at future 5Gbps rates, Burns said.

But in the server arena, Hewlett-Packard, IBM and others are developing PCI-X version 2.0 that they believe will be adequate for their systems for the foreseeable future, said keynoter Hetzler, a researcher at IBM Almaden. One-hundred million PCI-X slots may be available in the market by 2004, Hetzler said. IBM started shipping servers using PCI-X in December.

"I think it's a tricky process trying to determine when to extend a technology and when to abandon it for something new," Hetzler said. "I predict we will have versions of PCI-X beyond the 533MBps [of PCI-X 2.0]. I think this market is too big to switch technologies too soon."

Interoperability spec

Meanwhile, a new working group looking to hammer out a PCI-X/PCI Express interoperability specification convened for the first time via a telephone conference Friday (May 31). The group hopes to deliver a spec in about four months. Silicon from that effort might not arrive until the third quarter of 2003.

Some members of the group hope to leverage the spec to create PCI Express silicon that would essentially include an existing PCI-X ASIC and about a million gates of bridging silicon.

That spec could launch some players into the market for PCI Express chips early, albeit at a slight cost and performance penalty. It is also expected to provide an early and important avenue for PCI Express silicon to be tested in existing PCI-X servers, especially since several OEMs have said they will not build PCI Express directly into their servers.

Some PCI-X backers have been calling for the formation of the interoperability working group since last December, but only recently gained the needed cooperation of Intel. "It should have been started a long time ago, but all of a sudden there's a sense of urgency [from Intel]," according to one source close to the interoperability talks who asked not to be named.

PCI Special Interest Group representatives hosting the meeting told engineers they would have to make their own choices about which of the two specifications they will adopt in their products. "We in the PCI SIG [Special Interest Group] provide specs. We are not in the business of telling you what to do with them," said outgoing PCI chairman and president Roger Tipley, a senior server engineer with HP.

? Rick Merritt

EE Times

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