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RTL-to-GDSII flow shows signs of maturity

Posted: 05 Jun 2002 ?? ?Print Version ?Bookmark and Share

Keywords:RTL-to-GDSII? design flow? Design Automation Conference? Cadence Design System? Magma Design Automation?

The RTL-to-GDSII design flow will take center stage at next week's Design Automation Conference in New Orleans, as several vendors show new technologies intended to solidify an all-in-one flow.

Cadence Design Systems Inc. and Magma Design Automation Inc. will demonstrate continuing improvements in their all-in-one suites, with Cadence showing a polished version of SP&R (synthesis, place and route) IC implementation suite and Magma previewing its silicon virtual-prototyping tool, Blast Prototype. Synopsys Inc., too, is rumored to be on the verge of announcing two tools for the front end of its RTL-to-GDSII flow.

Meanwhile, a handful of startups, including Atrenta, Icinergy, InTime and Tera Systems, will demonstrate floor-planning and silicon virtual-prototyping point tools that users can plug into the larger flows. And two vendors, Synplicity and Incentia, will show how their synthesis technologies can be plugged into these flows. Also, Monterey Design Systems Inc. will be showing how its Sonar product, when combined with third-party synthesis tools, provides a "complete" physical-synthesis capability.

Over the last three years, many of the big vendors in electronic design automation have focused their R&D efforts on all-in-one RTL-to-GDSII tool suites that tie together logical or register-transfer-level design and synthesis with floor planning, placement and routing.

The idea is that linking these tools tightly in a single flow will better equip engineers to deal with the timing, power and signal-integrity issues of deep-submicron fab processes by letting them write RTL and perform synthesis, placement and routing in a single pass. The result will be to get designs out the door more quickly, it is believed.

In the last year, EDA juggernauts such as Cadence and Synopsys, and newcomers like Magma and Monterey, have made headway in establishing all-in-one flows through both internal development and company acquisitions. But, so far, no single vendor has established itself as the clear leader, offering best-in-class technologies at every point in the flow.

Vital component

One vital component has been missing, said Gary Smith, EDA analyst with research firm Gartner Dataquest: a silicon virtual-prototype tool, a product that Smith believes will become the new handoff point for the ASIC design flow. The silicon virtual-prototype tool will sit between the electronic-system- and register-transfer levels, he said, and at an RT floor-planning stage, the prototype will be almost silicon-accurate.

The silicon virtual-prototype tool functions as a cockpit that collects information like timing, signal integrity and power from the various tools in the implementation tool suite, and creates a viable floor plan based on that feedback and on fab constraints. After establishing a suitable floor plan, users drive the design through to GDSII using the silicon virtual-prototype tool.

"There's a race on to see who can create a real silicon virtual-prototype tool," said Smith. "At this DAC [Design Automation Conference], we will see companies making big inroads, but none of them are quite there yet."

Smith said that of all the tools he previewed before the show, he is particularly encouraged by the progress Cadence and Magma have made to their respective all-in-one tool flows. Smith also cited Tera Systems, which he said has made strides toward offering a silicon virtual-prototyping tool that can fit into larger third-party flows.

At DAC booth No. 1316, Cadence will demonstrate a polished version of its SP&R IC implementation suite. To this latest version of SoC Encounter, the company has added several capabilities, such as faster synthesis, postroute timing-driven signal integrity optimization, multi-CPU routing, power planning, data path optimization and low-power synthesis.

Magma, too, is actively improving its flow, and in DAC booth No. 2842 will show an early version of its Blast Prototype silicon virtual-prototyping tool. The new tool can be tacked onto the Blast Chip RTL-to-GDSII environment or used standalone in other vendors' flows. Currently in the alpha-test phase, Blast Prototype won't likely be ready until late in the year.

Magma's offering reads RTL code and generates an "early silicon performance" report that gauges the post layout timing feasibility of a design based on the virtual-prototype placement and routing. The tool also generates an "endpoint gain report" that identifies problematic paths.

From these reports, designers create their design constraints, drive floor planning and partition their designs into functional blocks. They then drive the design through synthesis, place and route, checking that the design conforms to the prototype at each step.

Check before floor plan

Tera Systems Inc., for its part, has introduced TeraForm-RTL Design Consultant, a new version of its TeraForm prototyping tool targeted at RTL developers. With it, architects and RTL developers can check the RTL for semantics, timing, area, congestion, synthesis constraints and layout implementation-related issues as they are developing an RTL floor plan, the company said. Tera will be putting this tool through its paces at DAC booth No. 2032.

Meanwhile, at booth No. 2232, IC floor-planning tool startup InTime Software Inc. will be demonstrating an RTL floor planner and a gate-level floor planner to complement its architectural-level floor planner. With the Time Planner and Time Builder products, the company said, users of InTime's Time Architect floor planner will be able to refine their IC floor plan successively through all the major steps of an IC design process using one company's technology.

Where Time Architect solves problems at the concept level and lets users determine whether they really want to build a product, Time Planner and Time Builder handle later chores. Time Planner lets designers refine the floor plan in greater detail, at the RT level feeding into synthesis. Post synthesis, users can refine the floor plan even more, at the gate level, with Time Builder.

Also at DAC, in booth No. 2555, Icinergy Software will demonstrate version 3.0 of its SoCarchitect prototyping tool, which features a new timing-analysis engine. Its hierarchical timing-budgeting algorithm extracts path information from the tool's virtual router to accurately predict delay through global routes. This allows SoCarchitect to determine early in the design cycle, at the RT level, whether a design will meet timing closure, the company said. The design can then be tuned as necessary, thus reducing downstream iterations.

In the Icinergy flow, designers begin with an abstract timing model and gradually assign clock domains and timing constraints as they refine the design. SoCarchitect's timing-audit capability can ensure that constraints are consistent and complete. Designers can use these constraints, presented in SDC format in version 3.0, to drive synthesis. Timing results can be back-annotated from an initial synthesis run and employed to fine-tune the timing model, according to Icinergy.

Unlike many competing tools, SoCarchitect does not have a built-in synthesis engine, but rather accesses third-party synthesis tools to ensure timing matches between SoCarchitect and the synthesis tool the designer will ultimately use in synthesizing the RTL to gates.

As other vendors showcase floor planning and silicon virtual prototyping, startup Atrenta Inc. will be showing, in booth No. 2925, a new logical prototyping feature for its SpyGlass IC prototyping tool. The feature allows users to create a logical prototype early in the design process to help determine what intellectual property (IP) could be used.

Users feed Verilog or VHDL to SpyGlass SoC, then use rules from Atrenta's constraints library to set up such specifics as clock hookups, resets, test and access requirements. The tool uses SpyGlass' fast synthesis engine to obtain information about the entire system-on-chip (SoC) design and the IP blocks considered for incorporation into it. If the tool finds violations, it highlights the problems in the RTL to help users pinpoint their source and speed the debug process. Atrenta will be showing the tool at DAC booth No. 2925.

ASIC synthesis

Also at DAC, Incentia Design Systems Inc. will demonstrate its first physical-synthesis tool, Design Craft Pro. The company said that the tool's synthesis, timing and placement engines are tightly integrated and, together, represent the key value of the tool.

For its part, Synplicity Inc. will be demonstrating timing-driven partitioning technology new to the latest revision of its Synplify ASIC tool. The Multi-Point synthesis technology allows users to partition their designs based on functionality and timing instead of gate counts. This, claims the company, yields better-quality timing and area results, faster run-times, the ability to handle very large designs, ease of project setup and constraint entry, and intelligent handling of IP blocks.

The upgraded version of Monterey's Sonar physical-prototyping tool boasts a new, detailed gate-level placement capability. The technology allows Sonar, when used with an RTL ASIC synthesis tool, to perform physical synthesis, the company said.

Monterey claims that Sonar will produce physical prototypes in less that 1/25 the time it takes to fully place and route a large chip. The tool provides feedback on timing, area and power, as well as delivers logic restructuring, technology mapping, cell sizing, buffer insertion and postplacement optimization.

? Michael Santarini

EE Times





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