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Agilent EoS mapper integrates serdes, CDR, framers

Posted: 04 Jun 2002 ?? ?Print Version ?Bookmark and Share

Keywords:hdmp 3002? ethernet over sonet? mapper ic? sonet/sdh network ic? datacom ic?

The HDMP-3002 Gigabit Ethernet over SONET (EoS) mapper IC from Agilent Technologies Inc. integrates a serdes, CDR, and OC-3 to OC-48 framers, required to efficiently format data for SONET/SDH networks.

The 664-pin CBGA device is the second member of the company's multi-protocol IC which take protocol-independent traffic and map it into SONET/SDH, providing a solution for loading enterprise data traffic onto a SONET/SDH metro infrastructure.

The EoS mapper provides access to SONET/SDH overhead collection, allowing carriers to manage their networks. It also offers the performance monitoring carriers require without the need for costly layer-3 processing.

The chip provides full-duplex mapping of Fast Ethernet and Gigabit Ethernet frames encapsulated into STS-48/12/3 SONET/SDH payload using the generic framing procedures (GFP), frame delineated HDLC, or the link access procedure-SDH (LAPS) protocol.

It can connect up to four Gigabit Ethernet feeds into one STS-48/STM-16 (2.488Gbps), four STS-12/STM-4 (622Mbps), or four STS-3/STM-1 (155Mbps) channels.

A virtual concatenation feature allows service providers to dial up "bandwidth on demand" for customers, allocating bandwidth data streams as small as STS-1 (51.8Mbps) granularity. Virtual concatenation eliminates the bandwidth inefficiency and long provisioning delays of legacy SONET/SDH transport networks.

The Layer-2, single-chip solution is implemented using a 0.185m CMOS process with a 1.8V core, and 2.5V and 3.3V I/Os.

The HDMP-3002 is priced at $475 in 1,000-unit quantities.

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