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Denali IP core manages SoC memory bandwidth

Posted: 06 Jun 2002 ?? ?Print Version ?Bookmark and Share

Keywords:databahn? memory controller ip core? soc design? memory bandwidth management? ddr sdram?

Denali Software Inc. has enhanced its Databahn memory controller IP core by adding an ability to regulate and optimize memory bandwidth in an SoC design. The core can now manage the memory access of multiple on-chip computing clients to the finite bandwidth of off-chip DRAM.

SoCs usually require high-bandwidth access to off-chip memory, and access that memory in two ways: via an on-chip bus like Amba or via dedicated ports. Sonics Inc., another IP provider, offers a core that manages memory access to on-chip buses. Denali's enhanced Databahn core accommodates the Amba bus and proprietary buses.

The Denali core enables designers to optimize an SoC's memory controller configurations without matching the bandwidth and latency requirements of individual processing units with memory, and without readjusting the memory access to processing elements when trying to support new memory types, the company said.

"Databahn resolves all of these conflicting requirements," said Mark Gogolewski, COO and VP of engineering at Denali Software. "This new Databahn core contains a completely configurable multi-port arbitration unit, integrated to a configurable DRAM memory controller."

The solution allows dynamic and granular trade-offs between high-priority, low-latency requests and overall optimized bandwidth. Furthermore, Databahn is supported by online performance analysis tools at the website, where system architects can prove out their SoC approach with a variety of the DRAM types.

The Databahn core supports more than 4,500 different memory components, including the latest DDR-SDRAM, FCRAM and RLDRAM, the company said.

Nicolas Mokhoff

EE Times

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