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Motorola adopts Cadence AMS Designer for next-gen SoC designs

Posted: 11 Jun 2002 ?? ?Print Version ?Bookmark and Share

Keywords:Motorola? AMS Designer? SoC? HCS12 microcontroller? internal voltage regulator?

Cadence Design Systems Inc. has signed an agreement with Motorola to provide the latter's Semiconductor Products Sector division with the Cadence AMS Designer simulation tool suite, which will be used for next-generation SoC designs.

The first Motorola product to benefit from AMS Designer is the HCS12 microcontroller, a mixed-signal SoC which includes HCS12core (16-bit), 10-bit ADC, internal voltage regulator, PLL and as memory Flash, EEPROM and RAM.

The Transportation & Standard Products Group within Motorola has been seeking a Verilog-AMS capable mixed-signal simulator that could enhance multiple aspects of the design process for large and complex designs. The group selected AMS Designer because Motorola felt it has the ability to improve the architectural design and simulation of the chip through the design and implementation of the individual modules within Motorola's existing digital verification environment.

The Cadence AMS Designer is based upon the OVI standard Verilog-AMS language and incorporates VHDL-D, Spice and Spectre circuit simulator. The AMS Designer also extends the Cadence analog and digital design flows for complex mixed-signal and SoC ICs.





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