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Downturn crimps ASIC design starts

Posted: 12 Jun 2002 ?? ?Print Version ?Bookmark and Share

Keywords:ASIC? semiconductor? Design Automation Conference? OEM? PLD?

The ASIC industry has taken an unusually hard battering in the latest semiconductor industry downturn, with the number of design starts dropping along with revenue, according to analysts from Gartner Dataquest, speaking Sunday (June 9) prior to the opening of the 39th Design Automation Conference.

Unlike previous downturns, design activity did not continue through the slowdown, said chief analyst Bryan Lewis. "The fact was that there was a substantial drop in system revenues, and that caused a drop in ASIC design starts," he said. "Instead of continuing design activity, system OEMs delayed or canceled projects."

Starts of cell-based ASICs and of PLD-based projects both fell about 3 percent last year, Lewis said. And with recovery in the end system markets still elusive, those project starts are unlikely to grow this year, he said. Starts of gate-array designs fell even more rapidly, on a continuing trend away from the gate array methodology.

Much of the problem could be traced back to the dot-com implosion, according to Lewis. "In 2000, about 48 percent of ASIC designs came from the communications industry, and about 42 percent of those designs were specifically in networking equipment applications." Thus the sudden glut of hardware in the networking world impacted ASIC starts heavily.

If Lewis saw a bright spot, it was in the shift from less ambitious ASICs toward SoC designs. "About half of ASIC designs are now SoCs, and that percentage is growing rapidly," he said.

? Ron J. Wilson

EE Times





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