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STMicro Flash memories target LPC bus interface

Posted: 13 Jun 2002 ?? ?Print Version ?Bookmark and Share

Keywords:m50lpw002? m50lpw040? m50lpw080? flash memory? low pin count bus?

STMicroelectronics has introduced a family of Flash memories targeted at the industry-standard low pin-count (LPC) bus interface used in computer motherboard architectures, and are designed to store system and video BIOS codes.

The LPC family includes the 2Mb M50LPW002, the 4Mb M50LPW040 and the 8Mb M50LPW080, and supplements the company's Firmware Hub and ISA bus compatible Flash memories.

Manufactured using the company's 0.185m technology, the memories operate from a 3V to 3.6V supply for program, erase, and read operations, while an optional 12V supply is available to speed up programming. They have a maximum active current of 20mA and standby current 100mA. Data retention is placed at a minimum of 20 years.

The 32-pin PLCC devices have a program/erase controller with an embedded byte program/erase algorithm and a program/erase suspend feature that allows a program or erase operation to be suspended to allow read operations in other blocks.

A quadruple byte programming option is also available to speed up programming in a manufacturing environment. Typical programming time is 10ms per byte, while the typical block erase time 750ms for a 64KB block.

The LPC devices feature both hardware and software block protections that are provided by write protect pins and lock registers which define the individual block protection status. All the functions are available via the LPC interface.

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