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Denali launches IP core for optimized memory access

Posted: 13 Jun 2002 ?? ?Print Version ?Bookmark and Share

Keywords:Databahn core? IP core? SoC memory systems? DRAM memory? DDR-SDRAM?

Denali Software Inc., a provider of memory system designs, has launched Databahn core for SoC bandwidth allocation.

Databahn is an IP core designed to reduce the time designers spend on developing and testing SoC memory systems. The configurable and programmable core manages and optimizes the memory access of multiple on-chip computing clients to the finite bandwidth of off-chip DRAM memory.

Denali explains that SoC designers spend considerable time designing systems to allocate off-chip memory access to the various on-chip processing units-all based upon the unique bandwidth and latency requirements of individual processing units. The task is further complicated by the need to adjust the memory access to the processing elements during the design process, and the need to support new and emerging high-speed DRAMs such as DDR-SDRAM, FCRAM, and RLDRAM.

According to Mark Gogolewski, COO and VP of engineering at Denali, Databahn resolves these conflicting requirements because it contains a configurable multi-port arbitration unit, integrated to a configurable DRAM memory controller that allows granular trade-offs between high-priority, low latency requests and overall optimized bandwidth. Additionally, Databahn is supported by online performance analysis tools at where system architects can prove out their SoC approach with a variety of the new and different DRAM memory types.

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