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Tools are the bottleneck, says EDA panel

Posted: 14 Jun 2002 ?? ?Print Version ?Bookmark and Share

Keywords:A panel discussion on the utility of EDA tools at the Design Automation Conference here came to a consensus within a short period of time.?

A panel discussion on the utility of EDA tools at the Design Automation Conference here came to a consensus within a short period of time. While under strict admonition by the session chair to avoid knocking the EDA industry, users and vendors on a panel designed to point out design flow bottlenecks nonetheless identified EDA tools as the most culpable.

The design flows are seriously broken, concluded users like John Szetela, manager for tools integration at Advanced Micro Devices Inc., and Hilton Kirk, manager of physical design at Philips Research Labs. "Late changes in the design flow are inevitable?and the automated design flow is too slow to accommodate them," explained AMD's Szetela. The point tools for analyzing post-layout parasitics?what Szetela called "the Big Four": IR drops, electro-migration, antenna effects and signal integrity?conflict with timing analysis tools.

If it weren't for FPGAs and "silicon platforms," the use and re-use of proven hard blocks and generous guardbanding, a new system depending on custom designs would barely get out on time, said AMD's Kirk. The reliance on point tools (rather than integrated flows) has produced engineers whose skill set is either "short and fat" or "tall and thin," he said.

"The tool flow is not straightforward; there are lots of little tools," conceded Patrick Groeneveld of Magma Design Automation Inc. "Even if the user is the bottleneck, the tools should have been better." He suggested minimizing tool-to-user interaction. "Analog design is always manual," he said. "The rest needs to be brutally automatic."

But panelist Ron Collett, president of Numetrics Management Systems, a Santa Clara consultancy, refused to join the finger pointing. "Events' cause bottlenecks," he insisted. Schedule overruns (84 percent of the perceived bottleneck) are due to unforeseen specification changes, and inadequate deployment of engineering resources, he said. He suggested that measurements of effort and productivity could be modeled against quantitative measures for design complexity. Such measurements would provide a useful metric that could be used by management to assess staffing requirements and avoid system-on-chip (SoC) project stumbles.

Tighter tool integration supported by a universal database was high on the wish list of panel participants. AMD's Szetela, for example, was hostile toward the single-vendor design flow. Philips' Kirk called for support of Cadence's OpenAccess initiative.

The worst thing that can be said about the EDA industry is that it is immature, concluded Lavi Lev, a technology vice president with Cadence Design Systems Inc. "If design flows seemed clogged, it was because of missing standards?though the situation was not helped by EDA guys trying to tell chipmakers what their problems are," he said. "Good teams manage to create SoC. In the end, nothing has failed?it just hurts a lot."

? Stephan Ohr

EE Times

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