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Better designs would spur recovery, NEC chairman says

Posted: 14 Jun 2002 ?? ?Print Version ?Bookmark and Share

Keywords:Design Automation Conference? semiconductor? DRAM? fables? SoC?

Manufacturing prowess and savvy marketing pulled integrated device manufacturers (IDMs) out of previous recessions, but chipmakers will have to get better at designing system-on-chip (SoC) devices if they are to survive the current crippling downturn, according to NEC Corp. chairman Hajime Sasaki, speaking Tuesday (June 11) at the 39th Design Automation Conference.

Sasaki called the latest chip downturn a "nightmare" that prompted IDMs to consider new directions and management styles. The NEC chairman and former head of its chip-making arm is overseeing a massive restructuring of his company, including the spin-off of its semiconductor division.

This isn't the first time the chip industry has come face-to-face with fundamental change. In the 1980s, Japanese chip makers took the lead in process technology and manufacturing, particularly in the area of DRAMs. In the 1990s, larger chip makers and fabless chip companies started focusing on certain application areas where they could ply their strengths, Sasaki said.

Going forward, success will be determined by how well chip makers cull their design, intellectual property and manufacturing expertise to build complete SoC devices, he said.

"In the next decade there will be a new type of strategy for system LSI, one where design competence and process competence merge into one," Sasaki said.

"What we sell is not a chip but solutions," he added. "We have to change our way of thinking to ensure customer satisfaction."

There are many twists and turns on the road to system-on-chip bliss, however. One will be to persuade the design community to embrace the C-based behavioral language to drastically reduce the lines of code compared to RTL. It will also have to foster hardware and software co-design and better utilize chip resources like registers and memory, Sasaki said.

Signal-integrity problems also loom large, and today can hobble a chip designed for 500-MHz to the point where it only runs at 100-MHz. To address this difficulty, Sasaki touted "flexible parameter CMOS," wherein highly-integrated devices incorporate transistors with different voltage thresholds, low-voltage macros and new technologies like silicon-on-insulator.

"By integrating different devices on the same chip it's becoming possible to fit circuit performance for each application," Sasaki said.

Reuse of intellectual property (IP) cores is another major hurdle for chip makers, he said. RTL-level IP blocks have not been widely accepted to date because they are not versatile or reliable. But "behavioral IP" shows more promise, and can be scaled to provide both better performance and lower gate count simultaneously, Sasaki said.

Despite these changes, chip companies can't escape certain "unavoidable facts" about the chip business, he said. These include the assurance of more market turbulence in the future and having the perseverance not to abandon chip technology and customers when the next downturn hits.

Moreover, chip makers will have to change their management styles. These comments in particular appeared aimed at Japan's rigid management structure, which has been partly blamed for the country's economic woes of the last 10 years.

Sasaki said chip companies must learn to evaluate engineers objectively, stop hoarding their talents, a cultivate a "design-oriented culture," he said.

"It is time to abandon the policy of enclosure for designers and engineers," Sasaki said. No matter what a chip company aims for, "design competency rules the world," he said.

? Anthony Cataldo

EE Times

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