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Aldec extends RTL hardware accelerator capacity

Posted: 14 Jun 2002 ?? ?Print Version ?Bookmark and Share

Keywords:riviera ipt v12000? ic design? fpga design? rtl hardware accelarator? synthesis tool?

Aldec Inc. has announced the availability of the Riviera IPT v12000 functional RTL hardware accelerator that handles up to 12 million FPGA gates. It is claimed to reduce RTL design verification times by as much as 50 times, compared to traditional event-driven simulators.

Showcased at the 39th Design Automation Conference in New Orleans, the Riviera IPT can accommodate memories, DSPs, ASICs and other devices, and verifies legacy designs, EDIF-based IP cores, hardware devices and HDL blocks from a single design acceleration environment.

It supports VHDL, Verilog and mixed-language designs and includes interfaces to C, Verisity's Specman Elite "e" or Synopsys' Vera advanced testbench tools. Any synthesizable RTL code can be downloaded into the hardware accelerator allowing designers to reduce the system level design verification run times without changing their existing RTL design methodologies.

"With 12 million gates and available expansion, we have overcome the capacity issue, additional memory requirements and support for large number of clocks that most of our customers are dealing with today," stated Eric Seabrook, Riviera Product Marketing Manager for Aldec.

The hardware accelerator uses Aldec's Incremental Prototyping Technology to enable the designer to verify and optimize his or her design in manageable, smaller sized blocks according to project schedules.

Each block is verified in software by Riviera IPT's built-in event-driven simulator to allow for full signal visibility and complete debugging of modules before placing them in hardware. The verified module is then placed in hardware and remains "connected" to the remainder of the design that resides in software.

The verification tool then uses a patented closed loop technology to provide event-based communication between the software and hardware components through a PCI interface.

The Riviera IPT includes an IEEE VHDL, Verilog common kernel mixed simulator, Synplify Logic Synthesis, Dual Xilinx Virtex II 6000 hardware accelerator board with all the drivers and a design verification manager. The system can be configured for UNIX, Linux or Windows NT/2000/XP systems.

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