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Synopsys compiler handles >20 million gate designs

Posted: 14 Jun 2002 ?? ?Print Version ?Bookmark and Share

Keywords:floorplan compiler? physical compiler? routing tool? ic design? embedded system design?

Synopsys Inc. introduced at the 39th Design Automation Conference the availability of the Floorplan Compiler, a high-end hierarchical design planner that accommodates >20 million gate designs through smart partitioning, and enables designers to save time and money by creating high quality floorplans in fewer iterations.

The compiler uses a virtual flat approach that eliminates the ping-pong effect that normally occurs between chip-level and block-level floorplanning. This also enables critical floorplanning decisions such as partitioning, block shaping, macro placement, pin assignment, and feed-through optimization to be made in the full context of the chip, including blockages and routing hotspots.

Built using the same placement technology as the company's Physical Compiler, the Floorplan Compiler performs placing and trial routing of the design to understand its routing blockages and route congestion. Buffer insertion and pin and feed-through assignments are then created based on this route.

"We are in the middle of taping out a timing-critical six-million-gate set top box design with Floorplan Compiler. We've been able to converge on our partitions, pin assignments, macro placements and feed-throughs in a fraction of the time it took us on our previous design," claims Maynard Hammond, ASIC principal engineer, Subscriber Networks Sector, Scientific Atlanta Inc.

"Our very first floorplan was routable and met our timing milestone. So far, we've shaved six to eight weeks from our tapeout schedule thanks to Floorplan Compiler," he added.

The compiler also features automatic handling of channel-based and abutted designs to minimize design times while providing flexibility in implementation style.

Pricing for the Floorplan Compiler starts at $150,000.





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