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Toshiba enhances embedded DRAM with SOI wafer

Posted: 17 Jun 2002 ?? ?Print Version ?Bookmark and Share

Keywords:DRAM? silicon-on-insulator? SoC applications? epitaxial-Si? CMOS?

Toshiba Corp. has accomplished a breakthrough in embedding DRAM on silicon-on-insulator (SOI) wafers which ends the DRAM performance degradation typical of such integration. The new technology will be applied to high-performance SoC applications.

Toshiba's breakthrough hybrid wafer fuses the electrical characteristics of SOI and bulk wafer. The wafer's structure is achieved by removing part of the SOI layer and the buried oxide layer on SOI wafer and replacing it with conventional silicon by epitaxial-Si growth (SEG) technology.

The electrical characteristics of DRAMs embedded in the new hybrid wafers match that of DRAMs produced on bulk wafer with 180nm CMOS process technology. Toshiba is scheduled to introduce the hybrid wafer with 65nm process technology in 2005.





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