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Quickturn upgrades design verification system

Posted: 18 Jun 2002 ?? ?Print Version ?Bookmark and Share

Keywords:palladium? design verification system? ic design? ic design verification? ic verifcation?

Quickturn has upgraded its Palladium design verification system to provide higher simulation-acceleration performance and support configurations of 2-million to 128-million ASIC gates, as well as up to 64GB of memory and >8,000 physical I/Os for target system interfacing.

The system features a new high-speed channel between the workstation and Palladium, designed to lower inter-process latency and improve run-time performance by orders of magnitude over software-based simulation tools.

Software enhancements include a tighter integration with Cadence's NC-Sim and testbench automation tools TestBuilder and Verisity's Specman Elite, which streamlines debug at the transaction-level.

The upgrade also features a standardized IP card form factor, that interfaces physical IP cores within Palladium's IP-chassis to designs for both simulation-acceleration and in-circuit emulation.

The company claims that turnkey IP-cards with IP cores from ARM and TriMedia Technologies enable hardware/software co-verification at speeds where embedded software can be developed and tested.

The new Palladium configurations and software will be available for purchase as well as through the company's QuickCycles EXtended (EX) Access program. QuickCycles EX is an extension of QuickCycles that gives customers the option of remote access to Quickturn's latest technologies, or on-site access, with the equipment installed at the customer's facility.





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