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Cadence custom environment handles mixed-signal IC designs

Posted: 21 Jun 2002 ?? ?Print Version ?Bookmark and Share

Keywords:custom ic design? analog artist? virtuoso? asic design? mixed signal ic design?

Cadence Design Systems Inc. has introduced a mixed-signal design environment for custom ICs.

Version 5.0 of Cadence's Custom IC Design flow brings analog and mixed-signal simulation tools from its Analog Artist along with the Virtuoso custom layout editor into the digital ASIC design environment. The goal is to create an unbroken flow for large mixed-signal ICs, according to Craig Silver, VP at Cadence.

The software addresses the needs of large digital designs with critical analog and RF circuitry, said Silver. Predominantly analog IC designs use mixed-technology processes such as silicon germanium and very high-speed interfaces, typically above 2.5GHz.

The devices require hand layout to avoid noise, crosstalk and parasitics, Silver said. But they are small, ranging from 1,000 gates to 100,000 gates and 2mm to 4mm per side.

Predominantly digital designs with analog circuitry tend to be much larger, with 50,000 to millions of logic gates and measuring 10mm to 16mm per side. The analog portions of those circuits must fit into the design flows for big ASICs, which typically use large blocks of digital intellectual property.

The Custom IC Design environment introduced by Cadence at the 39th Design Automation Conference includes an "infrastructure for digital/mixed-signal ICs," said Silver. It includes a mechanism for moving large blocks of digital IP (including imported external IP) and what Silver called focused cockpits for subflows. The cockpit tools allow designers or design team members to create analog blocks, he said.

The analog tools include Analog Composer and AMS Designer for circuit entry, Spectre and Spectre-RF for time domain simulation, Virtuoso XL for custom layout, Neolinear Corp.'s NeoCell for sizing and Cadence's Chip Assembly packages for routing.

Silver offered a laundry list of benefits the new package would provide, including high-level language support (VHDL-AMS will be added to Verilog-AMS in the first quarter); improved process design kit availability, with more foundry choices; digital and analog cell characterization within Spectre; and inclusion of a placer and wire editor in Virtuoso XL to offer faster layout productivity.

All Cadence tools will support the OpenAccess database and will run on Linux by the first quarter, Silver said.

Stephan Ohr

EE Times





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