Hybrid architecture embeds Xilinx FPGA core into IBM ASICs

Undeterred by earlier false starts for programmable ASICs, IBM Corp. and Xilinx Inc. are embarking on a plan to jointly create an architecture that melds an FPGA core with a standard-cell ASIC methodology starting at the 90-nanometer process technology node. Expected to be ready to ship by 2004, the XBlue architecture is perhaps the most ambitious attempt thus far to create a market for hybrid devices.

The joint effort by the two market leaders says as much about the enormous design potential conferred by sub-100-nm chip designs as it does about the escalating cost to put it to use. Nonrecurring engineering fees at the 90-nm (0.09-micron) node?particularly the cost of producing the photomask set?will have risen to the point that many designers will have to lean on programmable "platform" ASICs that can be used again and again, the companies contend.

"The costs of ASICs and mask sets are getting higher and higher," said Wim Roelandts, president and chief executive officer at Xilinx. "When you looked at this space a couple of years ago?when it was a couple of hundred thousand dollars?and when you look at it today, when it's a million dollars, things are very different."

The companies say the 90-nm node is the best place to start because the gate density will be so great that embedded programmable-logic cores will have little consequence on chip size. One of the biggest stumbling blocks to embedded FPGAs so far has been that the FPGA portion of a design was disproportionately larger than the ASIC portion. Because FPGAs use active interconnect, they take up 10 times more area than ASIC gates.

Tom Reeves, vice president of custom logic at IBM Microelectronics, said embedded FPGAs only become practical below the 130-nm node. "You need to have a reasonable 10, 20 or 30 percent of the die for FPGA and use the majority of the area for standard cell," Reeves said. "In prior generations, you have been ridiculously blowing up the die size."

Designs in 2003

Under the agreement, Xilinx is developing a set of FPGA cores in densities ranging from 10,000 to 40,000 gates to be integrated in IBM's Cu-08 ASIC methodology. The companies expect designers to use between 20,000 and 100,000 FPGA gates per design, although the count can go as high as 400,000 gates.

The EDA software will be based on Xilinx's existing tools, although some modifications will be needed to integrate them into IBM's methodology. IBM will be responsible for the ASIC development and final product, including chip simulation, testing and diagnostics for the FPGA core. The companies said they expect to take on the first designs in 2003 and ship the first hybrid devices in 2004.

The partners say they can shave off hundreds of thousands of dollars in development costs for customers who choose this approach. Of course, the companies also stand to gain, since customers are more likely to place large ASIC orders if they can use the same design for multiple end applications without having to create a new mask set.

"I get manufacturing efficiency and pass that along to lower production costs. I'm much happier with fewer part numbers that run at higher volumes," Reeves said.

Xilinx, meanwhile, will be able to reap royalty payments for every device IBM ships that includes its programmable-logic core, and it gets to tap into a high-volume market that it couldn't otherwise reach. Xilinx claims the FPGA cores embedded into the ASICs will be small enough that they won't undercut its own standard-products business. "We don't have products with less than 50,000 gates," Roelandts said.

The agreement underscores a tightening relationship between leading ASIC supplier IBM and FPGA kingpin Xilinx. The two have been working closely for several years, starting with Xilinx's licensing of a PowerPC processor core and CoreConnect on-chip bus from IBM. Those elements are included in Xilinx's latest Virtex-2 Pro FPGA. Xilinx also uses IBM as a foundry to manufacture the FPGAs.

Cary Snyder, an independent chip analyst in San Jose, Calif., said the partners have been quietly working on the embedded FPGA technology for at least three years. "Both companies have had a boatload of engineers working on this and have spent millions of dollars getting to this point," he said. "I don't think they are overstating the potential this has."

Others, too, have recognized that potential, but so far the hybrid devices have failed to spark interest among ASIC designers. Observers have pointed to several reasons, including the huge disparities in speed, power consumption and density between FPGAs and standard-cell gates.

Embedded FPGAs in limbo

ASIC vendor LSI Logic Corp., which has licensed embedded FPGA cores from Adaptive Silicon, has shelved the embedded FPGA program it had introduced as part of its 0.18-micron ASIC technology. And FPGA vendor Actel Corp. has seen little demand for the embedded FPGA cores it has tried to sell through foundries.

Snyder said that previous attempts to combine standard-cell and FPGA gates were premature and that designers didn't want to risk moving to a new technology when they could still afford to make mask set changes and spin new silicon.

Even so, a handful of startup companies continue to pursue embedded FPGAs, and some, such as Leopard Logic Inc., claim they have customers.

LSI Logic, for its part, is keeping the technology in its back pocket and continues to explore ways to make ASICs more flexible. "I think having different types of programmability built into chips is going to become more important," said Wilfred Corrigan, the company's chairman and chief executive officer.

IBM and Xilinx said they are taking pains to make the technology bulletproof. Xilinx's FPGA core is architecturally similar to its Virtex FPGA fabric, but it has stripped out the embedded RAM in order to reduce the size and power consumption.

The FPGA core is being retrofitted with a new I/O structure. Reeves said he expects that the core will be able to connect to the rest of the system-on-chip design through IBM's CoreConnect on-chip bus.

Smooth detour

Xilinx said it can leverage its existing software tools, although some work still has to be done to ensure that designers can make a smooth detour into an FPGA flow. Specifically, the tool flow will have to partition the RTL to identify the FPGA code, execute a Xilinx flow and then translate the output to IBM's format, Reeves said.

While the announcement is aimed at ASICs, both companies have an opportunity to ply the technology for standard products. Xilinx already has plans to introduce standard, discrete products based on the same technology as the embedded FPGA core. "We will have products that have the same architecture and structure as this core," Roelandts said.

Snyder said it's likely that IBM standard products groups, such as its PowerPC division, will want to use the FPGA core to build system-on-chip devices with programmable hardware. "This would attract lower- and mid-volume players that can't afford an ASIC," he said.

Even larger customers have been requesting leading ASIC manufacturer IBM to include FPGA cores as a way to create silicon "platforms," or multipurpose chips that can can be tailored for different end applications by making changes to the programmable-logic portions. "Some of the large OEMs very explicitly asked for this capability," said IBM's Reeves.

Initially, IBM and Xilinx acknowledge that they will likely spend more time answering questions than taking purchase orders. Hybrid ASICs remain largely in the conceptual stage, and designers will want more details about the FPGA fabric, routing capabilities and early tapeout results before making any commitments.

Reeves expects designers will gradually warm to the embedded FPGAs in much the same way that many have come to accept embedded DRAM.

"We're going to have to get them thinking," he said. "It will take a while for the light bulbs to go on."

? Anthony Cataldo

EE Times