Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Closing the custom gap

Posted: 01 Jul 2002 ?? ?Print Version ?Bookmark and Share

Keywords:asic design? custom circuit? standard-cell asic? kurt keutzer? tool talk?

Why are custom circuits three to eight times faster than equivalent ASICs, and what can be done to narrow the difference? That's the topic of an important new book: Closing the Gap Between ASIC and Custom.

The book's authors are Kurt Keutzer, professor of electrical engineering and computer science at the University of California at Berkeley, and David Chinnery, a UC Berkeley graduate student. Some notable authors in academia and industry also contributed chapters.

The book targets ASIC and ASSP designers who want higher performance, as well as custom designers seeking better productivity. And it's a wake-up call to EDA tool developers, since it notes that many necessary improvements, such as continuous cell sizing and process impact analysis, lack commercial tool offerings.

The book starts with a comparison of synthesizable ASIC processors to custom processors and explains the three- to-eightfold performance gap. One factor is pipelining, which is difficult to fully exploit in ASICs because they don't have tight control over timing overhead. Another is process variation, which ASIC designers try to predict through worst-case numbers, leaving a lot of performance on the table. Yet another is the custom designers' use of dynamic logic, which is not commercially available to ASIC designers.

Custom designers will always have greater control over timing overhead, transistor and wire sizing, manufacturing processes, and the like. But there is much ASIC designers can do to get closer to full-custom performance, and that's what the bulk of the book discusses.

Several chapters offer tutorials on improving ASIC performance through better microarchitectures, reducing timing overhead, using high-speed logic and getting the best results from a given process. A number of subsequent chapters look at emerging design tools and techniques. Contributors include authors from Silicon Perspective, Tensilica, Celestry, Cadabra, Zenasis, IBM and Intel, as well as various universities.

The book concludes with several design examples that show how microarchitectures were developed for very high-speed ASICs. One, for example, shows how Texas Instruments achieved 550MHz in a standard-cell ASIC methodology.

The book focuses on timing performance rather than power, signal integrity and other deep-submicron concerns. But it's clearly part of a solution that could revolutionize ASIC design.

? Richard Goering

EE Times

Article Comments - Closing the custom gap
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top