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Micrel clock buffers provide ultra-low skew, jitter, redundant switchover

Posted: 03 Jul 2002 ?? ?Print Version ?Bookmark and Share

Keywords:sy89830u? sy100ep15v? pecl? lvpecl? clock fanout buffer?

The SY89830U and SY100EP15V high-speed, PECL/LVPECL clock fanout buffers from Micrel Semiconductor meet ultra-low skew, jitter and redundant switchover requirements in SONET/SDH communications systems, high-end enterprise server applications, and ATE systems.

The SY89830U is a fully differential PECL/LVPECL 1:4 fanout buffer with a differential 2:1 MUX input. This device is guaranteed to operate down to 2.3V, thus making it suitable for low-voltage, 2.5V PECL clock distribution systems.

The 3.3V/5V SY100EP15V is a 1:4 PECL/LVPECL fanout buffer with a 2:1 MUX input, but one of the inputs is single-ended, and the other input to the MUX is differential. It also includes a VBB reference voltage for single-ended inputs or ac-coupled applications.

Both fanout buffers include a synchronous enable function that force all outputs into a fixed logic state without any possibility of short, runt pulses.

In order to maintain extremely tight timing budgets over all system conditions, the SY89830U and SY100EP15V ac-parameters are guaranteed over temperature and supply voltage, the company says. Maximum frequency is >2.5GHz, within-device skew is <25ps, propagation delay is <450ps, and output rise and fall time is <225ps.

Pricing for the buffers start at $5.60, in quantities of 1,000. Both are offered in a small (5-by-4.4mm) 16-pin TSSOP, and specified over the -400C to 850C industrial temperature range.





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