TranSwitch offers single-chip solution for DS3/DS1/E1 access systems

TranSwitch Corp. has introduced the TEPro device, a RISC processor-based SoC with embedded DD-AMPS firmware and host API, to support next-generation channelized DS3/DS1/E1/DS0 applications targeting wireless access, MSAPs, computer telephony, TDMA over Packet, and Echo Cancellation Unit.

The 46-lead PBGA device occupies a 27-by-27mm footprint and supports either one DS3, 28 DS1, or 21 E1 line interfaces.

The on-chip processor is addressed by the host via an abstracted, encapsulated, message-based API, which eases the need for low-level programming and software integration efforts, while accelerating product development and time-to-market.

TEPro integrates an M13/G.747 multiplexer including a DS3 framer with full C-bit functionality to support clear-channel DS3. It also has a 28-channel DS1 framer, a 21-channel E1 framer, a 28-channel DS1/E1 cross-connect, and a 672-by-4,096 channel non-blocking DS0 cross-connect for grooming, concentration, switching and multiplexing.

It has a message mailbox FIFO, multi-channel HDLC for Layer 1 and 2 SS7 (including FISUs) and ISDN-PRI signaling, MVIP and H.100/H.110 TDM bus interfaces, and the on-chip RISC processor.

TEPro is priced at $148 per unit in 1,000-unit quantities.