Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Verification startup wants everyone to go 'formal'

Posted: 10 Jul 2002 ?? ?Print Version ?Bookmark and Share

Keywords:tempusquest? interface checker? ic verification? RTL verification? EDA?

A new approach to RTL verification is under development at Tempus Fugit Inc., an EDA startup launched by former Cadence Design Systems developers. The company is preparing an interface protocol checker that promises to make formal techniques accessible to the average engineer. Tempus Fugit, founded in 1999 as a consulting firm, plans a formal launch of its TempusQuest Interface Checker in the fall.

"We're trying to provide a solution that's easy for the customer to use," said Vigyan Singhal, president and chief executive officer at Tempus Fugit. "We have a product you can take off the shelf and use to verify designs for compliance with standard interfaces. You don't even have to write assertions."

At Cadence, Singhal developed technology for the "Heck" equivalence checker, used in that company's Affirma formal equivalency checker. He has published more than 50 papers, holds two U.S. patents and teaches extension classes in design verification at the University of California. Joe Higgins, Tempus Fugit's vice president of engineering, was the lead software engineer for the Heck project.

Tempus Fugit is a "bootstrap" operation with no venture-capital funding, Singhal said. But even without a marketing department, it has cultivated some key early-adopter customers, including Aarohi Communications, Ikanos Communications, Nvidia, PLX Technology, Redback Networks and Sun Microsystems. These customers are providing feedback that's being used to strengthen TempusQuest, Singhal said.

To use TempusQuest, Singhal said, a designer need only provide Verilog register-transfer-level code. The tool is a static checker that requires no test vectors or simulation runs. "If you have a software constraint that's necessary to prove compliance with the protocol, you may have to add that to the script," he said.

The output is a listing of errors; users can look at waveforms and debug from those. TempusQuest checks for compliance with interfaces such as PCI, AGP, HyperTransport, USB, Fibre Channel, Ethernet, IEEE 1394, ARM Amba, IBM CoreConnect, ATM-PHY Utopia, DDR-1 and -II, and SP14/SP15.

Singhal said the tool has found "hard corner-case bugs" that would not be found in emulation or simulation. One example involved a PCI master missing a parity error on the bus that occurred in the penultimate cycle of a long burst transaction. The master's write buffers were full then, and the slave inserted a wait cycle in the previous cycle.

The technology behind the product, and the Verilog parser, were developed in-house, Singhal said.

?Richard Goering

EE Times

Article Comments - Verification startup wants everyone ...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top