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Startup preps router for leading-edge designs

Posted: 11 Jul 2002 ?? ?Print Version ?Bookmark and Share

Keywords:EDA? Cadence Design System? Synopsys? standard-cell routing-tool? standard-cell ASIC design?

A tiny EDA startup out of Research Triangle Park, N.C. hopes of giving vendors like Cadence Design Systems Inc. and Synopsys Inc. a run for their money in the standard-cell routing-tool market.

The eight-person ViASIC Inc. was co-founded in 2000 by Bill Cox, who built EDA tools for QuickLogic and Synplicity Inc., Tom McKay, who worked on Avanti Corp.'s Milkyway database, and Laura Zavelson, formerly of Johnson & Johnson and Guidant Corp.

Until now, the company has had two place and route products?HybridMask and ViaMask?both of which focused on the array market.

But now the company has recruited Max Lloyd, formerly of Avanti and ASIC International Inc., as its new president and chief executive officer and is using the routing technology from its gate array products as the core of a new router for bleeding-edge standard-cell ASIC design.

"At ASIC International, we were customers of Avanti, Magma and Monterrey. Each of those products had deficiencies," said Lloyd. "So when I left ASIC International, I sat down with the ViASIC folks and said, 'What do we need to do to make this router available for ASIC designers?' "

Lloyd said that the company is now creating the router and expects to have the product release ready by the end of the year.

"It was encouraging walking around the Design Automation Conference last June," Lloyd said. "There were half a dozen to a dozen companies offering optimization and placement tools, but really none had routers. The question is if you're a user of one of these tools, do you want to then take a $700,000 place-and-route tool just to do routing, especially if it is not the best router out there, or do you want to get a standalone router that really works for what you need? What we are offering seems to really fit very well with what the market needs."

Lloyd said the router will have a higher capacity, faster performance and will be directed at issues for designs in 130 nm and finer process technologies.

"Most of the routers on the market today, even some of the recent ones, were designed to route all of your signals to the outside of the chip to the pads," said Lloyd. "Now with flip-chip packages, you need to route to the inside of the chip."

Lloyd said that the use of phase-shift mask puts new constraints on a router. "If you do a wire jog, which is how you normally address antennae effects with routers, you throw Numerical Technology's phase-shift tool off. You also need more capacity and speed. These are problems that need to be addressed by next-generation routers. Most routers on the market today are old and fairly outdated," said Lloyd. "We plan on offering a router that will beat the competition in terms of capacity, speed and ease of use."

ViASIC is not yet ready to detail its product, but Lloyd said the company has nine patents on the router and that the product's main selling point will be its automatic partitioning of large designs, easy hierarchical reassembly of standard-cell, custom, memory and intellectual property blocks as well as its ability to perform both standard-cell and top-level assembly routing.

Lloyd said the company has secured $2 million from revenue and seed and series A funding, the latter of which came from an undisclosed corporation. The company will soon seek its first major round of venture funding as the company's new router gets closer to production, Lloyd said.

? Michael Santarini

EE Times





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