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ChipMOS develops high-speed wafer test technology

Posted: 16 Jul 2002 ?? ?Print Version ?Bookmark and Share

Keywords:wafer test? DDR DRAM? Teradyne? Tokyo Electron? FormFactor?

ChipMOS Technologies (Bermuda) Ltd has developed a high-speed wafer test technology that enables testing of 32 DDR DRAMs, running at 200MHz clock speed and 400Mb data rate, in parallel. The breakthrough project, financially supported by the Taiwan government, was realized through technological collaboration between ChipMOS and three of its major suppliers in this field- Teradyne, Tokyo Electron Ltd and FormFactor Inc.

"The high-speed wafer test technology is an important accomplishment as it reduces the cost of testing for our clients and increases the chip yields significantly," said S.J. Cheng, deputy chairman and CEO of ChipMOS/Bermuda.

"The key to this technology is that it helps uncover more known-good dies and eliminate defective chips before they go on for packaging or to the next process. As a result, we can integrate wafer level assembly and full contact wafer level burn-in to provide our customers with more comprehensive services. ChipMOS now has a pilot line for 200mm and 300mm wafers in place and a skilled engineering team ready to help customers moving to this technology. This technology is expected to further solidify our relationship with major customers" added Cheng.





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