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Lattice lands programmable-logic combo punch

Posted: 16 Jul 2002 ?? ?Print Version ?Bookmark and Share

Keywords:lattice semiconductor? ispxp? ispxpga? spxpld? programmable logic device?

In an effort to bridge the divide between different types of programmable-logic devices, on Lattice Semiconductor has announced a new architecture that combines the programming attributes of CPLDs and FPGAs.

The ispXP series of PLDs is based on SRAM technology, allowing the parts to be reconfigured an unlimited number of times. What makes them different, however, is the inclusion of E? cells, which allow nonvolatile reprogrammability.

Such programming attributes normally exist in different realms in the taxonomy of PLDs. Complex PLDs, which are based on nonvolatile E? technology, are known for highly deterministic timing and routing but are generally less dense and are susceptible to wear after a few thousand programming cycles or less.

SRAM-based FPGAs, meanwhile, are usually denser and usually contain embedded-memory blocks. But they require the use of an external PROM device for programming, which makes them slow to come to life at power up and poses a potential security threat by exposing the bit stream.

Yet a number of customers want to have both programming techniques at their disposal in a single product, creating an opportunity for a "third way," said Steven Laub, president of the Lattice Semiconductor.

"We see that 80 to 90 percent of customers are saying that they would like to have it. One-third of them will say that they absolutely will choose these products," Laub said.

Lattice aims to deliver this new class of CPLDs and FPGAs starting this quarter. The FPGA version, dubbed ispXPGA, contains many of the same features of today's mainstream FPGAs and can also be self-configured in less than 200?s by using its E? bits.

The product family marks Lattice's second foray into FPGAs since it acquired the Orca product line from Agere Systems last December. While Orca addresses those applications that need high-speed I/O built into hard ASIC gates, ispXPGA will be positioned more as a generic FPGA architecture, Laub said.

The nonvolatile cells can be programmed using the IEEE Test Access Port or through a device programmer system, and comply with the IEEE 1532 programming algorithm. Additionally, the nonvolatile bits can be programmed in background mode during operation. The ispXPGA will support 1,000 E? programming cycles.

SRAM control

The SRAM memory controls the logic functionality. There are three ways to reconfigure the SRAM: downloading from the E? memory; through the IEEE 1532 mode; and using a CPU through a 33MHz, 8-bit parallel port.

Otherwise, ispXPGA resembles an FPGA. The programmable function unit (PFU) is based on a four-input lookup table structure and includes dedicated hardware for adders, multipliers, MUXs, and counters.

These programmable units are enmeshed in a segmented routing scheme that includes several types of connections between individual programmable function units, long connects across the chip (horizontally and vertically) and feedback signals in each PFU without using external routing.

To transmit data at high speeds across a backplane, batteries of serial interfaces are capable of 850Mbps of bandwidth by using clock and data recovery with two types of encoding schemes.

For transmitting signals on a circuit board, the family supports source-synchronous mode, which transmits clock and data in parallel. At each corner of the device are a pair of PLLs that have low jitter and good input jitter tolerance characteristics, said Gordon Hands, strategic-marketing manager at Lattice.

Like most of today's newest FPGAs, the ispXPGA architecture has blocks of embedded memory. These come in the form of strips of block RAM within the PFU array and adjacent to the I/O.

The embedded-memory blocks can be configured by width and used single- or dual-ported or as a FIFO. If more memory is neededor if a designer wants to use lesseach PFU can double as distributed RAM.

The amount of block RAM, which is proportional to gate density and cost, will range from 92Kb to 414Kb. If distributed RAM is counted, the potential memory content can grow by another 30Kb to 246Kb.

The inclusion of embedded memory distinguishes Lattice's second product family, a line of CPLDs based on the same ispXP architecture incorporating both volatile and nonvolatile programming characteristics.

The spXPLD family is made up of an array of multifunction blocks that can be programmed as logic or dual-ported memory, as a FIFO or as a ternary content-addressable memory. Lattice promises to deliver CPLDs that include between 128Kb and 512Kb of embedded memory.

CPLDs normally lack embedded memory because it is too costly to implement, but Lattice says it has found a way around this problem. "The question is how to combine gates used as logic efficiently with memory," said Hands.

In logic mode, the multifunction blocks are built to take in wide inputs68 from the routing and, optionally, another 68 from an adjacent multifunction block. The inputs flow into an AND array and are combined with OR gates in a product-term-sharing array, which sends out 160 product terms on every output.

Lattice plans to introduce this quarter a 1.25 million system-gate FPGA and 150,000 system-gate CPLD based on its ispXP technology. They are expected to ship in volume in the fourth quarter at $345 and $17.75, respectively, based on shipments of 1,000 units or more. Lattice plans three derivatives for both the CPLD and FPGA families by the first half of 2003.

Anthony Cataldo

EE Times





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