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Endeavor delivers co-simulation solution for Virtex-II Pro

Posted: 01 Aug 2002 ?? ?Print Version ?Bookmark and Share

Keywords:endeavor intertech? xilinx? cosimple? virtex ii pro? fpga co simulator?

Endeavor Intertech Corp. has announced the availability of the CoSimple hardware/software co-simulating solution for Xilinx Corp.'s Virtex-II Pro FPGAs, containing the IBM PowerPC 405 processor core.

A part of Endeavor's Unified Simulation product line, CoSimple contains the company's TransAccurate instruction set simulator, interactive debugging capabilities based on the GNU gdb interface, and a cycle-accurate Virtual Bus Model.

The CoSimple solution verifies most difficult-to-test hardware components and it interfaces to the free GNU tools available through Xilinx pre-targeted to the Virtex-II Pro and the PowerPC 405 core. The GNU gdb debugger provides the essential user interface to the co-simulating model, with complete support for source debugging, breakpoints, interrupts, and memory access.

Aside from simulating instructions for the debugger, CoSimple provides the inter-process communication and synchronization between the software debugger and the hardware debugging environment. This enables hardware developers, for example, to run test vectors, break on a specific location, and compare resultant waveforms.

The company claims that CoSimple features synchronization and communication with hardware simulators such as ModelSim Verilog and VHDL products, and provides virtually the same co-verification capabilities.

The Virtex-II Pro CoSimple solution is available immediately on the Solaris platform, and will be available soon for Windows PCs.

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