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WEDC DDR SDRAM occupies less board space

Posted: 01 Aug 2002 ?? ?Print Version ?Bookmark and Share

Keywords:white electronic designs? ddr sdram? synchronous dram? dynamic ram? random access memory?

White Electronic Designs has announced the release of 128MB DDR SDRAM MCPsin 16Mx 64 and 16Mx72 configurationsthat are designed to complement high performance memory controllers, and are available at speeds of 200MHz, 250MHz, and 266MHz.

Each DDR SDRAM is housed in a 219-ball PBGA, saving 40 percent board space over a comparable discrete approach, and is claimed to have a lower profile than other high-density memory approaches. It also reduces I/O connections by up to 19 percent, and provides reduced inductance and capacitance for low noise performance.

Designed using a CMOS process, the devices operate in 2.5V systems. Each chip is internally configured as a quad-bank DRAM with a synchronous interface. The devices use an internal pipelined architecture to achieve high-speed operation and allow the column address can be changed every clock cycle.

The MCPs are suitable for a wide range of telecom, datacom, and embedded applications. Each is available in commercial, industrial, and military temperature ranges.

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