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Pentek offers FPGA receiver, design kit

Posted: 07 Aug 2002 ?? ?Print Version ?Bookmark and Share

Keywords:pentek? gateflow? fast fourier transform? fpga receiver? fpga design kit?

Pentek Inc. has announced the release of the GateFlow family of extendible FPGA products that include GateFlow installed cores featuring the company's streamlined Fast Fourier Transform (FFT) implemented on an FPGA-based dual-channel wideband receiver, and the GateFlow FPGA Design Kit to facilitate custom algorithm development.

"These latest FPGA devices feature built-in hardware multipliers, a large pool of configurable memory, and plenty of system gates and logic blocks," said Rodger Hosking, VP of Pentek. "Even after all of the standard data formatting and interfacing functions for the module is incorporated, these FPGAs still offer substantial available resources for signal processing functions."

The company's Model 6235 dual channel, 12-bit, 100MHz wideband digital receiver features a GateFlow FPGA FFT engine suitable for front end applications in signal processing systems.

It includes two complete acquisition and receiver channels in a VIM-2 (Velocity Interface Mezzanine) module compatible with Pentek's 429x series PowerPC and C6000 VME processor boards.

The Model 6235 can be equipped with either the XC2V1000 or XC2V3000 FPGA from the Xilinx Virtex-II family, offering logic densities of 1 or 3 million gates, respectively.

Utilizing proprietary block memory architecture, the GateFlow FFT executes a pipelined complex 4k-point radix-4 FFT in 10.245s - four times faster than the time to collect the 4k input points at a 100MHz sampling rate. The execution speed for the 1k-point complex FFT is 2.565s - which is four times faster than real-time at 100MHz.

An optional Hanning (or alternate) windowing function can be applied at each of the four complex input streams to reduce the rounding and truncation errors. An optional power calculation is included, which is available at the FFT output. Further, an averager stage adds the two outputs of the 50 percent input overlap FFTs, improving SNR characteristics.

The Model 4953 GateFlow FPGA Design Kit provides users with design information, software files, and utilities for extending FPGA-functions into Pentek's FPGA-based VIM and PMC narrowband and wideband digital receivers, ADCs, and FPDP I/O modules.

Additionally, the kit allows users to implement pre-processing functions such as convolution, framing, pattern recognition, decompression, delays, beamforming, decoding, time stamping, averaging, and summation.

The Design Kit includes the software project used in Xilinx Foundation to create all of the standard factory functions of the product, such as device and bus interfaces, data formatting, clocking, and control.

The Model 4953 GateFlow FPGA Design Kit for user-defined algorithms is priced at $1,500, while the Model 6235 Dual Channel Receiver with 1k GateFlow FFT starts at $11,995. The Model 6235 with 4k GateFlow FFT starts at $12,995.

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