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Silicon Metrics tool designs, models I/O

Posted: 14 Aug 2002 ?? ?Print Version ?Bookmark and Share

Keywords:silicon metrics? siliconsmart cr? siliconsmart i/o? ic design? formal verification tool?

Silicon Metrics Corp. hopes to follow up the success of its SiliconSmart CR standard cell library development tool with the release of a tool that helps characterize, model, and verify the electrical spec compliance of a design's I/O.

The SiliconSmart I/O tool will serve Silicon Metrics' traditional customer base of library designers and modelers, plus design engineers who need to account for I/O characterization changes during the design process, said Callan Carpenter, president and CEO of Silicon Metrics.

"Unlike standard cells, which can be characterized prior to having a specific design context, I/Os are very sensitive to the environment in which they are used," said Carpenter. "They are sensitive to the specific pad ring design, package, and complex loads on the target PCB."

"So if you want to get an accurate model and do accurate compliance specification, you need to get chip designers involved to get these types of information into the design and modeling process," he added.

The tool has a broad feature set that suit the needs of I/O modelers, I/O designers, and SoC engineers, said director of product marketing Dennis George.

"Most people get their I/O from multiple sources, and one of the first things they need to do is verify that the I/O they have will meet the specification they are designing to," said George.

"They also need to generate accurate models - to get accurate results when you put those models in the design flow verifying that the results you are returning represent the environment that they actually operate in."

SiliconSmart I/O combines automated electrical compliance validation, "Spice-accurate" characterization and vendor-certified model generation, the company said. The compliance validation feature provide a report that covers all operating corners, detailing instances of non-compliance to electrical specifications, Silicon Metrics said.

Guruprasad Rao, co-founder and principal engineer at Silicon Metrics, said the tool's measurement acquisition technology accounts for mixed-signal entities within I/O cells.

The tool automatically verifies analog characteristics and measurements such as state voltage, drive current, differential sensitivity, hysteresis, crossover voltage, and non-monotonic waveform detection, he said.

"For users generating models, the tool performs much in the same way as our other characterization tools," said Rao. "It goes through Spice simulation, sets up all the stimulus to acquire all these measurements that go into an HDL model - an accurate abstraction of a cell. These models will be used in a static timing run."

Automatic check

For I/O designers and SoC engineers working to ensure a design complies with published electrical specifications, Silicon Metrics has built into the tool compliance rules that automatically checks if a given I/O design complies with industry standards and characteristics.

This cuts down the often tedious job of gathering standard specifications from many sources and checking each on to ensure design compliance, Silicon Metrics said.

The tool currently supports electrical specification compliance validation for USB low-speed, full-speed, and LVDS cells.

Support for SSTL and USB High Speed will be available in Q4. Other I/O specifications, such as HSTL, I2C, I2S, PCI, PCI-X, and AGP, will be available in subsequent releases of the tool, the company said.

Licensing starts at $90,000, depending on configuration and customized functions.

- Michael Santarini

EE Times

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