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Cadence releases revised signal integrity tool

Posted: 15 Aug 2002 ?? ?Print Version ?Bookmark and Share

Keywords:cadence design system? celtic v.4? celtic? signal integrity tool? board design?

Cadence Design Systems Inc. has released a new version of its CeltIC signal integrity solution with greater capacity, performance and accuracy than the previous version of the tool. Cadence said Version 4.0 can handle more than 5 million gates running on a 32-bit workstation.

The company also claims to have improved the accuracy of the tool, which can model the nonlinear slew degradation on victim nets that affect the rise-and-fall delays of receiver cells. Another new feature of the tool is its support for the BSIM4 and MOS9 device models.

Cadence said it has also tightened the integration of CeltIC with its SoC Encounter and Silicon Ensemble Corp.'s PKS products to allow users to analyze and repair crosstalk issues throughout the design flow.

According to the company, CeltIC 4.0 creates crosstalk repair files that drive the in-place-optimization engines of SoC Encounter and Silicon Ensemble PKS to implement fixes such as resizing victim drivers, inserting buffers, spacing aggressors away from victims, and shielding failing nets.

CeltIC 4.0 includes support for 32-bit Linux and IBM AIX OSs, as well as 64-bit workstations from Sun Microsystems Inc. and Hewlett-Packard Co.

- Michael Santarini

EE Times

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