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NEC chairman urges design-centric road to recovery

Posted: 16 Aug 2002 ?? ?Print Version ?Bookmark and Share

Keywords:soc? nec chairman? dac? Japanese chip industry? behavioral ip?

Manufacturing prowess and savvy marketing pulled integrated-device manufacturers (IDMs) out of previous recessions, but chipmakers will have to get better at designing SoC devices if they are to survive the current, crippling downturn, NEC Corp. chairman Hajime Sasaki told the 39th Design Automation Conference.

Sasaki called the latest chip downturn a "nightmare" that prompted IDMs to consider new directions and management styles. The former head of NEC's chip-making arm, Sasaki is overseeing a massive restructuring of his company, including the spin-off of its semiconductor division.

This isn't the first time the chip industry has come face-to-face with fundamental change. In the 1980s, Japanese chipmakers took the lead in process technology and manufacturing, particularly in the area of DRAMs. In the 1990s, larger chipmakers and fabless chip companies started focusing on certain application areas where they could ply their strengths, Sasaki said.

Merged 'competence'

Going forward, success will be determined by how well chipmakers cull their design, intellectual property (IP) and manufacturing expertise to build complete SoC devices, he said.

"In the next decade, there will be a new type of strategy for system LSI - one where design competence and process competence merge into one," Sasaki said.

"What we sell is not a chip but solutions," he added. "We have to change our way of thinking to ensure customer satisfaction."

There are many twists and turns on the road to SoC bliss, however. One will be to persuade the design community to embrace the C-based behavioral language to drastically reduce the lines of code compared to RTL. Also, it will have to foster hardware and software co-design and better utilize chip resources like registers and memory, Sasaki said.

Signal-integrity problems also loom large and can hobble a chip designed for 500MHz to the point where it only runs at 100MHz. To address this difficulty, Sasaki touted "flexible-parameter CMOS," wherein highly integrated devices incorporate transistors with different voltage thresholds, low-voltage macros, and new technologies like silicon-on-insulator.

"By integrating different devices on the same chip, it's becoming possible to fit circuit performance for each application," Sasaki said.

Reuse of IP cores is another major hurdle for chipmakers, he said. RTL-level IP blocks have not been widely accepted to date, because they are not versatile or reliable. But "behavioral IP" shows more promise and can be scaled to provide both better performance and lower gate count simultaneously, Sasaki said.

Despite those changes, chip companies can't escape certain "unavoidable facts" about the chip business, he said. These include the assurance of more market turbulence in the future and having the perseverance not to abandon chip technology and customers when the next downturn hits.

Cultural change

Moreover, he said, chipmakers will have to change their management styles. That comment appears to be aimed at Japan's rigid management structure, which has been partly blamed for the country's economic woes of the past 10 years.

Sasaki said chip companies must learn to evaluate engineers objectively, stop hoarding their talents and cultivate a "design-oriented culture."

"It is time to abandon the policy of enclosure for designers and engineers," Sasaki said. No matter what a chip company aims for, "design competency rules the world," he said.

- Anthony Cataldo

EE Times





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