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Cadence launches Asian symposium on nanometer technology

Posted: 21 Aug 2002 ?? ?Print Version ?Bookmark and Share

Keywords:Asia Cadence Technology Symposium? nm-scale design? EDA? IC design? PCB?

Cadence Design Systems Inc. has slated the first annual Asia Cadence Technology Symposium (ACTS) for its customers in the Asia-Pacific region. ACTS "02" is expected to identify nanometer design challenges and present methodologies and tools specifically designed to address them. The schedule for ACTS "02" is August 20 in Beijing, mainland China, August 23 in Shanghai, mainland China, August 27 in Hsin Chu, Taiwan and August 30 in Seoul, South Korea.

Cadence says that as industry innovators increasingly implement nanometer-scale designs, design teams are focusing on wire-centric strategies to create massively complex ICs in an acceptable timeframe. Strategies that are not clearly focused on rapid wire creation, optimization and analysis are destined to fail. According to the company, ACTS is an opportunity for engineers, designers and managers working in electronic design to learn what's happening in the EDA industry and at Cadence.

In addition to Cadence technologists, speakers at ACTS '02' include distinguished leaders from the EDA industry. Topics include Cadence's solutions for system-level design, wireless design, custom IC design, digital design, logic design, PCB design, system verification design, IC packaging design, and Cadence's hierarchical RTL-GDSII flow incorporating Silicon Virtual Prototyping.





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