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Axis adds assertion checking to emulation/acceleration

Posted: 21 Aug 2002 ?? ?Print Version ?Bookmark and Share

Keywords:axis systems? hardware platform? processor? semiformal tool? simulator?

Axis Systems Inc. has devised a way to run assertions efficiently on its hardware platforms and thereby speed up assertion checking and, ultimately, the overall verification process. New technology from the hardware-assisted verification company lets users run assertions on Axis acceleration and emulation products.

With the Assertion Processor module, Axis tools run assertion checks at least 1,000 times faster than running the same checks on a simulator or workstation, said product-marketing manager Jason Andrews. Axis' emulation customers will get the module for free; for acceleration customers, it is being sold as a $45,000 upgrade, he said.

At the same time, 0-In Inc. said it has tailored a version of its CheckerWare semiformal tool to allow Axis and 0-In customers to run assertions on Axis platforms and perform assertion-based verification at acceleration and emulation speeds.

Assertions are statements that document engineers' assumptions and the properties of a given design. Engineers use assertions to cross-check a design's actual vs. intended behavior and to formally specify intended behavior so the engineers can verify that an electronic system is acting according to their specifications.

Typically, engineers hand-write assertions or plug them into the HDL versions of their designs from a library. They then run the HDL and checkers in a simulator to find bugs and problem areas-typically a time-consuming process.

Event-based scheme

To speed the run-time, engineers can opt to run their HDL and assertions in an emulator or accelerator instead. But conventional emulation systems don't allow engineers to accurately monitor the status of assertions or the larger verification runs.

Key to the Axis speedup, Andrews said, is its use of an event-based "interrupt-driven architecture" instead of a cycle-based "polling architecture," which too frequently passes commands from the emulator to the simulator running on a workstation via an application programming interface.

Andrews said a polling meth-od typically checks assertion at several intervals during the emulation process to discover whether assertions are failing. At each polling point the emulation stops, accesses (via the API) a workstation running a simulator, runs a check and then moves to the next polling point. This method is slow and can often miss the source of a bug if it happens to fall evenly between two polling checkpoints, he said.

"Polling has huge overhead associated with it," Andrews said. "If you have 10,000 assertions in a design, that means you probably have to read 10,000 bits out of an emulator and then do a calculation to see if anything has changed."

Andrews said an event-based interrupt-driven architecture does not perform checks on the workstation but actually runs the assertion checks on the hardware. Axis' Assertion Pro-cessor scans the design until it finds an interrupt or assertion failure, and then-and only then-accesses a workstation to run a thorough check.

"Throughout the design there are white boxes containing assertions," said Andrews. "During simulation those are constantly being checked and when one of those assertions fails, it will trigger a bit in the assertions processor, causing an interrupt. The interrupt will send a 'service routine' off to the workstation connected to the emulator, telling the engineer of the problem. After the engineer has noted or remedied the problem, it will then go back to the point of the interrupt and continue simulating and checking for errors."

The company ran the event-based interrupt-driven approach and cycle-based polling approach on one of its hardware systems and found the interrupt approach yielded on average a 4x run-time improvement over the cycle-based polling approach.

Waveforms on demand

Axis said the Assertion Processor technology can also be configured to trigger waveform viewing-VCD on demand-only when it detects problem areas, which saves even more run-time.

Andrews said that Axis' Assertion Processor will eventually support all popular assertion methodologies: declarative assertions using a library of Verilog monitor modules (Open Verification Library), procedural statements using a Verilog assert construct (SystemVerilog 3.0), formal property languages (Vera) and pseudocomment directives. But the initial version supports declarative assertions in the OVL, and pseudocomment directives from 0-In's CheckerWare libraries.

Kurt Takara, product manager at 0-In, said the companies worked together to ensure they created a streamlined assertion environment in which users can reuse the same assertions throughout the design and verification flow.

Takara explained that when developing designs, users can first run their assertions during simulation and then, when the design moves on to emulation, transfer those same assertions to the emulator or accelerator, using the 0-in interface software to locate the source of problem areas in the design.

"One of the benefits of the CheckerWare libraries is that we were able to transfer them into a synthesizable Verilog that can be mapped directly onto FPGAs in the Axis hardware systems," said Takara. "As the assertions do fire, the information is transferred to our database so users can use our viewer to debug and track the structural coverage information."

Takara claimed the assertions will not interfere with the Verilog syntax or require any changes to the emulator and accelerated simulator. "It is all transparent to the users and it looks the same in acceleration simulation and emulation as it does in just simulation."

The CheckerWare library currently contains more than 30 industry-standard networking, memory and system-on-chip interfaces from 0-In such as HyperTransport, PCI-X, Amba, AGP, Utopia and DDR SDRAM, he said. Takara added that the company has not solidified its licensing price for what it is calling the 0-in/Axis Solution, but it will likely be $50,000.

Steve Wang, vice president of marketing at Axis, said the assertion support is the latest in a series of upgrades expanding the versatility of Axis' platforms.

"We offer emulation, acceleration, and recently we have added support for code coverage in emulation as well as support for behavioral constructs," said Wang. "With this release we are adding support for assertion-based verification, showing the versatility of our RCC technology."

- Michael Santarini

EE Times





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