Tower Semiconductor adopts PDF Solution technology

PDF Solutions Inc., a provider of semiconductor process-design integration technologies and services, has partnered with Tower Semiconductor Ltd on a program to enhance the yield and performance of 0.185m CMOS process technology at Tower's Fab 2.

This program will require the implementation of a range of PDF's technologies in a broad scale, to prepare Tower's new Fab 2 process technology achieve maximum yield from all of its process-modules and to speed yield ramp for a wide range of semiconductor products. By utilizing PDF's technologies, Tower hopes to avoid typical product-specific yield loss mechanisms that are characteristic of fabrication facilities manufacturing many different products.

Tower's Fab 2 facility, currently prototyping 0.185m products, is scheduled to begin volume production by the end of 2002. The facility is expected to have a monthly capacity of 33,000 units of 200mm wafers.

"The use of PDF's methodology, characterization vehicle test chips, process analysis software, and yield simulation tools will provide a high level of process flexibility, intelligent customization, accelerated yield ramp, and high-target yields to our Fab 2 customers," said Ron Niv, manager of Tower's Fab 2.