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VeriSilicon platform optimized for SMIC CMOS process

Posted: 27 Aug 2002 ?? ?Print Version ?Bookmark and Share

Keywords:Standard Design Platform? CMOS process? memory compilers? I/O cell library?

VeriSilicon Microelectronics Co. Ltd has released the Standard Design Platform optimized specifically for Semiconductor Mfg Int. Corp.'s (SMIC) 0.185m CMOS process, which includes memory compilers for single port and dual port SRAM, diffusion programmable ROM, standard cell library, and I/O cell library. The platform has been proven in silicon through SMIC's Silicon Shuttle Prototyping Service.

"Our 0.185m ramp-up strategy requires the availability of the Standard Design Platform including cell libraries, memory compilers, and semiconductor IPs," said Richard Chang, president and CEO of SMIC. "We have been working closely with VeriSilicon and are pleased with their technical strength. This library's timing performance, low power consumption and high area density will allow our business to grow significantly by attracting many new design projects."

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