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ASIC vendors heed call for virtual prototyping tools

Posted: 29 Aug 2002 ?? ?Print Version ?Bookmark and Share

Keywords:asic? virtual prototyping tool? rtl? physical design? eda?

If time is money and product development budgets are being slashed, it follows that the time it takes to design and tape out a custom chip should fall too. That is no easy task as leading-edge process grows more complex, ASIC providers turn to new tools for aid.

Tool vendors have been talking about the need for virtual prototyping for some time, and it appears their ASIC customers are starting to listen. Virtual prototyping refers to a general class of EDA software that gives designers more visibility into physical layout during RTL creation so that they can spot timing problems before physical design.

One company that has found religion in virtual prototyping is Agere Systems Inc., which recently announced a deal to provide the First Encounter virtual prototyping tool from Cadence Design Systems Inc. Since the move to 0.185m design rules, it is no longer advisable for ASIC designers to rely solely on traditional wire load models to meet timing constraints. Using the traditional logical design and ASIC handoff model, it could take five to 10 design iterations before the timing issues can be resolved, said Wes Reid, strategic marketing manager for Agere Systems.

Goal: First-time hit

That should start to change now that the company is offering First Encounter as an adjunct to its ASIC design kit. "If the customer implements First Encounter as successfully as we anticipate, our goal is first-time success," Reid said. That should cut total design time by an average of six months, he added.

Under the agreement, Agere will lend First Encounter free to customers that agree to use Agere's ASIC design services. The Cadence-Agere agreement lets Agere's customers use the software for six months and two 90-day extensions. However, Reid said customers can use it essentially for as long as they need.

What's more, customers that use First Encounter are not bound to a Cadence-defined design flow. In fact, Agere uses Synopsys Inc.'s place and route tools (which Synopsys acquired in its purchase of Avanti Corp.) for back-end design, Reid said.

The deal is unusual because Agere can give copies of the Cadence-licensed tool to its own customers free. Cadence ordinarily sells tools directly to users.

This could signal a new selling strategy for the EDA industry. "Agere is the first one we have done this kind of business arrangement with," said Eric Filseth, vice president of marketing at Cadence.

ASIC vendor NEC Electronics Inc. has also taken up the virtual-prototyping mantra, partnering with Tera Systems Inc., whose TeraForm design planner converts RTL code into a structural abstraction for modeling logic, layout and timing. Other ASIC vendors using the TeraForm RTL design planner include LSI Logic Corp. and Fujitsu Ltd.

- Anthony Cataldo

EE Times





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