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SiS adopts Cadence technology for graphics IC design

Posted: 29 Aug 2002 ?? ?Print Version ?Bookmark and Share

Keywords:silicon virtual prototyping technology? First Encounter? graphics IC? tapeout? design flow?

Silicon Integrated Systems Corp. has standardized on Cadence Design Systems Inc.'s silicon virtual prototyping technology, the First Encounter, for the design of complex graphics ICs.

First Encounter's successful management of timing-driven placement issues was critical to the fast tape-out of SiS' six million-gate, 3D graphics IC. This new chip from SiS supports a 16-bit, bidirectional data bus at 533MHz operating frequency.

First Encounter was used to create a silicon virtual prototype, a near tapeout-quality implementation of the chip which included detailed routes. The prototype gave the design team visibility into the full chip's timing and routability at the very beginning of the physical design cycle. First Encounter has now been standardized in SiS' latest design flow.





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