Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Synopsys to acquire IC design verification firm

Posted: 30 Aug 2002 ?? ?Print Version ?Bookmark and Share

Keywords:SoC designs? Verilog simulator? hardware description language? Co-design SUPERLOG?

Synopsys Inc. has signed a definitive agreement to acquire all outstanding shares of Co-Design Automation, a privately held verification company focused on improving the designer's ability to create and verify SoC designs. The combination of Co-Design's technology with Synopsys' VCS Verilog simulator is expected to enable the delivery of next-generation hardware description language (HDL) solutions.

Co-Design is the developer of SUPERLOG, a language technology that extends the standard Verilog HDL with programming techniques and advanced verification and behavioral modeling capabilities that allow users to evolve their existing design and verification methodologies.

"The addition of Co-Design Automation to Synopsys comes at the very moment that SystemVerilog, the next-generation Verilog language, is coming about," stated Aart de Geus, chairman and CEO of Synopsys. "The combination of Synopsys' recent VCS 7.0 release, SUPERLOG technology, and the Accellera SystemVerilog umbrella will drive the state-of-the-art of RTL design and verification forward in very short order and decisively impact design productivity."

Article Comments - Synopsys to acquire IC design verifi...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top