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Sequence, UMC address interconnect inductance issues

Posted: 05 Sep 2002 ?? ?Print Version ?Bookmark and Share

Keywords:Sequence Design? self inductance parasitic modeler? interconnect? Columbus-RF? RF circuits?

Sequence Design and UMC have partnered to complete the first silicon correlation of an interconnect self inductance parasitic modeler. With this development, UMC customers developing technology at 150nm and below are expected to encounter fewer failures in their analog and digital designs due to interconnect issues.

Tuned specifically for high-frequency designers, Columbus-RF features modeling capabilities for RC and inductance in RF circuits. The tool's tight integration with the industry-standard Cadence Analog Design Environment and physical verification tools ensures ease of use and ease of adoption.

UMC and Sequence developed a methodology to ensure accuracy of Sequence's Columbus technology. Tests were performed on a total of 30 die at 150nm with plans for similar tests at 130nm and 90nm, each containing 25 unique interconnect self inductance structures. The s-parameters were then measured and converted to inductance values and correlated with the extracted interconnect self-inductance parasitic values. In all cases, the extracted inductances were said to be reported within 10 percent of silicon-measured values.

According to Vic Kulkarni, Sequence president and CEO, this project sprang from a concern that both companies had about the effects of inductance on timing and signal integrity due to interconnect issues arising from new, advanced processes.

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