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Toshiba, Neolinear formulate new methodology for Soc design

Posted: 16 Sep 2002 ?? ?Print Version ?Bookmark and Share

Keywords:mixed signal soc? ams design methodology? toshiba? neolinear? neocircuit?

The design of the analog portion of a mixed-signal SoC is a recognized bottleneck for getting SoC products to market. The primary causes of this bottleneck are the lack of qualified analog design engineers and inadequate EDA tools for the analog designer. One of the most profound effects of the lack of analog design automation is the limited reuse that occurs in analog/mixed-signal (AMS) design. A new automation-based design methodology for AMS SoC design is introduced here. This new methodology enables design reuse while providing performance equivalent to conventional full-custom analog design methodologies.

Analog Cores are a key component in system LSI or SoC applications. At Toshiba, analog design engineers design core analog functions such as PLLs and ADCs. Using conventional design flows, the same level of design experience and effort is required to port these previously designed core analog functions, even when a similar process is used.

To reduce the effort required to port analog cores from one process to another, Toshiba is implementing a new AMS design methodology that enables significant analog design reuse. A benefit of this new methodology is that valuable AMS design engineering resources previously needed for porting can be shifted to the design of new value-added analog cores.

Circuit & layout design

The time required to do circuit design and the quality of the results are strongly dependent on the skill of the designer. An experienced designer is able to find a good solution efficiently. In the case of a junior designer, many design/simulate/update schematic iterations are needed to obtain a design that meets the necessary performance specifications at all required operating and process corners. This takes a significant amount of time and requires considerable hardware and software resources. NeoCircuit improves this process by automating the circuit sizing process.

NeoCircuit automatically sizes any circuit topology - circuit schematic - to a set of specifications using commercial or proprietary simulators. This approach differs from other approaches, which are topology specific. NeoCircuit transforms an unsized circuit topology, annotated with critical device relationships, for instance, matching, into a sized circuit optimized to meet specifications. NeoCircuit uses the designer's simulator, test-benches and device models to evaluate automatically generated circuit solutions. This approach eliminates the need for back of the envelope calculations and a "good" starting point. Sizing may start completely from scratch, without any initial device sizing information on the schematic.

Sizing in NeoCircuit begins with annotating the schematic database with constraints, which includes defining critical device relationships, identifying independent variables and providing the target design specifications like total harmonic distortion (THD). Any number of simulations, including process and operating corner simulations, can be set up to measure the target specifications of the circuit. After sizing a circuit, designers can view trade-off curves, for example, between goals such as power and settling time, to quickly explore and select qualified circuits for the application. An important benefit obtained from using NeoCircuit is the capture of a designer's knowledge about the circuit in the form of constraints. Since these constraints are technology independent, the circuit may be reused easily.

NeoCircuit was used to size the cells comprising a segmentation and reassembly (SAR) ADC. The automatic sizing was done not only for nominal conditions, but also for process and operating corners such as high and low Vdd, as well as high and low temperature.

Analog design requires significant know-how such as determining which devices must match, signal isolation strategies and so forth. Even if the circuit design is excellent, the layout design can destroy the circuit performance if it is not implemented correctly. Therefore, the critical issue for the analog layout designer is to ensure that circuit performance is not compromised by the layout. As a result, significant experience is required to do analog layout.

At Toshiba, NeoCell was introduced as an automatic place & route tool to break through the productivity bottleneck for analog layout. Traditionally, manual analog cell layout starts with a sized circuit schematic and proceeds with one polygon at a time. The careful optimizations needed to handle the tight coupling between circuit and layout are managed only informally. This often means iterating over layout changes and repeatedly tweaking the geometry until no critical analog constraints are violated. A small cell may require days for layout. A larger cell may take weeks. Worse, vital electrical and geometric constraints specified during this tedious exercise are usually lost.

NeoCell fundamentally changes this tedious process. Its unique constraint-driven model captures these vital constraints and enforces them rigorously across all phases of layout. The result is that critical design information is unambiguously captured, enabling the design to be easily reused. For example, a layout may be automatically generated to meet different layout requirements or ported to a new manufacturing process.


The dramatic improvement in circuit and layout design productivity is clearly realized using the new design methodology. For the resistor DAC, the new methodology required as much time as the old methodology but produced significantly better results.

Using the old design process, four designer-weeks were required for circuit sizing compared to one designer-day using the new methodology. This design is particularly challenging because it contains seven stacked transistors in a 2.5V process resulting in minimal headroom and a lot of parameter for the designer to consider simultaneously.

The new methodology not only addresses this problem of complexity, but also enables the designer's intent to be captured as part of the design database. Since the new design is required to operate seven times faster than the original design, a direct comparison is difficult. However, an analysis by Toshiba's designers indicates that the new process provides results equivalent to or better than conventional, full-custom manual design.

Preliminary experience with the new design methodology indicates that an expert engineer performs the initial design best. This allows the significant know-how of the experienced designer to be captured as design constraints. Once the expert knowledge is captured in a reusable form, less-experienced engineers can easily perform design tasks such as porting because they can reuse this expert design knowledge.

By using NeoCircuit/NeoCell to develop a new, automated analog design flow, the analog blocks are becoming synthesizable. This new flow would benefit from additional capabilities. For example:

- Automatic topology selection

- Block-level circuit synthesis

- Automatic generation of behavioral AMS models

- Feed-forward of circuit information to layout, such as identification of parasitically sensitive nodes, net sizing to meet electromigration rules based upon simulated current, etc.

- Automated AMS floor-planning and hierarchical analog layout

- Signal path recognition and knowledge of current flow

- Fully automatic analog layout

Even though the automated analog flow is new compared to the conventional manual full-custom analog design flow, it provides major improvements in three important areas:

- Reduced design time for initial design compared to the conventional manual flow

- Equal or better design quality

- Reuse of AMS designs is now possible, resulting in the ability to leverage experienced designer's knowledge to achieve dramatic improvements in productivity

- Kazuhiro Oda

Mixed-Signal Design Manager

Toshiba Corp.

- Louis A. Prado

Senior Applications Engineer

Neolinear Inc.

- Anthony J. Gadient

VP Strategic Development

Neolinear Inc.

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