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Enabling VDSM SoC revolution with mixed-signal design

Posted: 16 Sep 2002 ?? ?Print Version ?Bookmark and Share

Keywords:vdsm? soc? analog circuit? idm? adc?

Driven by powerful technological and economic forces, the semiconductor industry is undergoing a fundamental transformation. These changes will not only transform the way future semiconductor products are developed but also change the underlying technology that will differentiate future semiconductor products.

As the large IDMs and foundries race to ready their newest 90nm processes, the design and EDA communities are struggling to overcome the challenges needed to generate economic value from the very deep sub-micron processes available at 180nm to 120nm. What are these challenges and how do we overcome them?

VDSM technologies allow levels of integration that were a mere dream less than five years ago. Previous process generations enabled the assimilation of digital functionality onto a single chip, leaving chips providing the remaining functions to be scattered about the system board. A significant fraction of this remaining functionality was analog or mixed-signal (A/M-S) in nature. The VDSM revolution allows the integration of all this functionality onto a single chip. This integration provides numerous potential benefits including reductions in system assembly cost, reduced power, increased reliability and so forth. As a result, new mixed-signal IC design starts will explode over the next three years.

Critical challenges

Unfortunately, the desired integration is problematic. The problem is rooted in the fundamental difference between A/D circuits. Unlike analog circuits, digital circuits scale well. As process features shrink, digital transistors get faster, cooler and cheaper. Since digital transistors must only register ones and zeroes, they are not impacted by differences due to process or temperature variation -- in effect, two similarly designed digital transistors that contain real-world defects will still be functionally equivalent.

In analog, however, even slight variations in the physical realization of two analog transistors or their operating environments will cause the transistors to behave differently, resulting in problems. Indeed, as feature sizes shrink, "mismatch" issues increase nonlinearly because small imperfections are magnified by the square of the reduction in device size.

In addition to mismatch, many other issues hamper the integration of analog and digital functions onto a single chip -- including substrate coupled noise, ohmic drop, and so forth. Two of the largest challenges are reductions in supply voltage and the lack of experienced designers.

A recent paper by Toshiba presented at the IEEE Electronic Design Process (EDP) workshop last April hints at the issues created by reductions in supply voltage. This paper discusses the design of a comparator circuit used in an ADC that took four weeks to migrate from a 0.255m process to a 0.145m process. This redesign required the designer to simultaneously determine 21 device properties -- width, length, m-factor for seven stacked transistors. Simultaneous resizing was required due to the minimal voltage margin provided in the new process.

As a result, the analog portion of an SoC is the most difficult part of a VDSM SoC to design. The analog portion typically represents about 2 percent of the transistors, yet takes up 20 percent of the chip area, 40 percent of the design effort and causes over half of all design re-spins. From the Toshiba paper, voltage scaling and other issues promise only to make the analog design problem harder.

Mixed-signal design automation

Achieving the increased margins available from mixed-signal SoCs, requires the analog, mixed-signal bottleneck to be addressed. Given the lack of experienced analog designers, A/M-S design automation is required to address this bottleneck.

Where is the EDA industry in addressing these challenges? To paraphrase a famous quote, the EDA industry does not have a complete A/M-S solution. It is not even at the beginning of having a complete solution. But it is, perhaps, at the end of the beginning. The major EDA vendors recognize the importance of the mixed-signal challenge. Lavi Lev, General Manager of Cadence's IC implementation division, acknowledges that analog design will prove crucial to SoC.

Neolinear, for example, develops design automation software for A/M-S design. NeoCircuit and NeoCircuit-RF automatically size analog, custom digital and RF circuits, dramatically improving design engineer productivity. NeoCell automatically places and routes analog cells. In combination, Neolinear's solution can provide an order of magnitude increase in design productivity.

Thus, the tremendous economic opportunity and dramatic technical challenges represented by VDSM SoC design is transforming the way semiconductor products are developed. Shifting the key differentiating technology for advanced semiconductor products away from digital to mixed-signal design and making A/M-S design automation tools an essential part of the next gen design flow. Indeed, if the world is an analog stage, then in the SoC world, digital will play only a bit part.

- Anthony J. Gadient

VP Strategic Development

Neolinear Inc.

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