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Zarlink SAR ICs integrate PLL, SRAM

Posted: 13 Sep 2002 ?? ?Print Version ?Bookmark and Share

Keywords:zarlink? mt90528? mt90520? segmentation and reassembly chip? tdm signal conversion?

Zarlink Semiconductor has announced the immediate availability of what they claim to be the industry's two most highly integrated AAL1 segmentation and reassembly (SAR) chips for TDM-to-ATM conversion.

By eliminating the need for up to six external devices in TDM-to-ATM designs, the MT90528 and MT90520 AAL1 SARs significantly reduce board space, lower system costs, and boost efficiency. Both are designed for applications in ATM edge switches, multiservice switches, broadband digital loop carriers, and ATM voice and media gateways. The lower-density MT90520 is also suitable for use in integrated access devices.

The MT90528 and MT90520 feature an on-chip, per-port PLLs for network synchronization and on-chip SRAM for channel buffering. The PLLs also allow each input to be synchronized to a different network clock, eliminating the need for up to four external framers.

They are also claimed to achieve a voice processing delay of 5005s, eliminating the need for external voice echo cancellers.

The chips receive constant bit rate traffic from DS1/E1 TDM ports operating at 1.544Mbps/2.048Mbps and convert it to 53-byte cells for transport over ATM networks. The MT90528 handles 28 DS1/E1 ports, while the MT90520 supports 8 ports.

In structured CES modes, the chips support Nx64Kbps service over up to 896 bidirectional VCs, with up to 128 TDM channels per VC.

The devices also feature Level 2 UTOPIA ports, operate either as UTOPIA "masters" or "slaves" in UTOPIA Level 1 mode, and transfer 8-bit or 16-bit data at clock rates of up to 52MHz. The ATM ports also act as multi-PHY (physical layer) in Level 2 mode.

The devices are offered in pin-to-pin compatible 456-ball PBGA packages and are priced at $200 for the MT90528 and $88 for the MT90520, both in 1,000-unit quantities.

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