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Multilink Tech FEC processor consumes 3.5W

Posted: 17 Sep 2002 ?? ?Print Version ?Bookmark and Share

Keywords:multilink technology? mtc6134? enhanced forward error correction? wrapper processor? fec?

Multilink Technology Corp. has introduced the MTC6134 Enhanced Forward Error correction (EFEC) digital wrapper processor that provides Metro applications with 8.5dB of net coding gain at 1x10-15 corrected BER, while dissipating 3.5W.

The bidirectional transport device also features full SONET/SDH section and line overhead processing, 10Gbps Ethernet performance monitoring, and G.709 Digital Wrapper termination and generation for 10Gbps systems.

Error correction is provided based on a block-oriented Reed-Solomon code RS (255,239) in addition to an optional proprietary FEC code that provides increased net coding gain with the same 7 percent overhead. The device supports single chip RS FEC to EFEC bridging and RS FEC to RS FEC regeneration.

Also integrated in to the 896-pin CBGA device are 10GbE PCS/MAC blocks for performance monitoring, support for a proprietary communications channel, and comprehensive FEC statistics with dedicated error signal outputs.

The MTC6134 occupies a 35-by-35mm footprint and is priced at $750 in sample quantities.

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