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Lattice rolls out new version of FPGA, PLD design tool

Posted: 19 Sep 2002 ?? ?Print Version ?Bookmark and Share

Keywords:lattice semiconductor? isplever? ic design? fpga design? pld design?

Lattice Semiconductor Corp. has announced the release of the ispLEVER v2.0 design tool suite, adding support for the company's ispXPGA and ispXPLD product families, as well as the ORCA FPGA and FPSC devices.

The suite contains the Module/IP Manager that speeds the design process by providing access to customizable IP modules suited for Lattice silicon or created by the user. The Module/IP Manager can also be used to speed the creation of common logical elements with the use of LPM (Library of Parameterized Modules)-like macros for design.

It also features the ispLEVER floorplanner, which provides control over the placement and routing of logic for ispXPGA designs. A color-coded GUI interface helps designers to easily identify and fix areas of routing congestion, locate and move design instances, and resolve critical timing issues.

As with previous version of the design suite, ispLEVER v2.0 still contains the Constraints Editor tool to allow the selection of I/O settings and pin assignments via a GUI drag-and-drop interface, and the Performance Analyst tool with SpeedSEARCH feature to enable complete flexibility to select and evaluate any device speed grade without design recompilation.

The ispEXPLORER tool is also included to help users find optimum design compiler settings by automatically performing multiple compiler runs and displaying the results in a spreadsheet format.

The ispLEVER tools support both Leonardo Spectrum and Synplify VHDL and Verilog synthesis tools, and the ModelSim RTL and Timing Simulation tool. They are available now for shipment and are priced at $995.

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