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Open-source tool offers HDL translation

Posted: 20 Sep 2002 ?? ?Print Version ?Bookmark and Share

Keywords:ocean logic? rtl vhdl translation? rts vhdl translator? verilog translation? verilog translator?

An open-source tool created by the director of a small silicon IP company translates a subset of RTL VHDL into Verilog. Vincenzo Liguori, director of Ocean Logic, said that more than 5,000 people have downloaded the free tool from the company's Web site.

Ocean Logic sells synthesizable VHDL and Verilog cores for JPEG, encryption, motion estimation, DCT/IDCT, and programmable one-cycle Huffman decoders. The company's JPEG technology has been acquired by InSilicon Corp., which in turn is being acquired by Synopsys Inc.

Liguori said he developed the translator because his customers need cores in both VHDL and Verilog. He said the tool has been used successfully to translate VHDL into Verilog for JPEG, triple DES, AES, and MPEG-4 cores.

The translator supports a "limited but useful" subset of VHDL, Liguori said - the same subset he uses in his own code for IP development. "It does not support all the features of VHDL, but it does a pretty good job of what it does. If the subset is supported, you can translate anything you like."

The translator, for example, does not support VHDL packages and only supports numerical types. It is for synthesizable code, not testbenches. The "readme" file notes that the tool could fail if there are misplaced comments and that there is a possibility it could translate illegal VHDL

Still, Liguori said he has received no bug reports - only requests for extending the VHDL subset. An upcoming update will do that, he said.

The translator is available for downloading at

- Richard Goering

EE Times

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