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Cadence adds Plato routing engine to design flow

Posted: 23 Sep 2002 ?? ?Print Version ?Bookmark and Share

Keywords:cadence design system? soc encounter? soc design tool? ic design tool? embedded system design?

Cadence Design Systems Inc. is upping the ante in the RTL-to-GDSII IC design tool game with the latest release of its SoC Encounter physical implementation tool. Cadence said v2.2 boasts a unified architecture with a single in-memory data model and user interface, and incorporates the NanoRoute routing engine Cadence gained early this year when it acquired Plato Design Systems.

The company is also releasing Nano Encounter, a lower-cost configuration of SoC Encounter that supports non-hierarchical designs up to 10 million gates.

Eric Filseth, VP of marketing at Cadence, said that v2.2 of SoC Encounter finally gives the company all the pieces it needs to offer a "completely unified architecture" that will let customers control the entire floorplanning-to-GDSII flow from the First Encounter cockpit.

Filseth described SoC Encounter as "really the successor to (the company's) Silicon Ensemble." Early versions of the tool included "scripts to interface First Encounter to Silicon Ensemble PKS so there was a real flow, but that was not the true platform integration. The new system is," said Filseth.

"We have all the engines running off a single cockpit, a single in-memory unified data model, single scripting environment, and single library environment. Basically, we think we have a completely unified architecture that the whole world is going to go to," Filseth said.

In v2.2, Cadence has replaced its longstanding grid-based routing engine, Warp Route, with the graph-based Plato NanoRoute engine. Incorporating NanoRoute into the flow was the key to creating the unified architecture. "NanoRoute becomes the flagship router for the company," said Filseth, who added that Warp Route is still included in version 2.2 to support legacy designs.

Thanks to NanoRoute, Filseth said that users of SoC Encounter will see a 5x to 10x improvement in both the capacity and the speed of the tool.

"Most routers today are grid-based routers and are good for routing bulk CMOS cells on regular intervals, but they are not so good at irregular intervals, irregular spacings, or routing things that do not fit onto a regular grid," said Filseth.

"To get around this, people have used shape-based routing, which is more flexible for doing designs that are not on a regular grid pattern. But shape-based routers have limited capacity. Graphic routers, like NanoRoute, combine the advantages of both," he added.

On-the-fly timing

Another gain over the previous version is that NanoRoute performs timing and signal integrity while it routes, Filseth said. "It is actually doing incremental signal integrity analysis and timing on the fly," he said. "In designs especially where you are worried about signal integrity, NanoRoute does a much cleaner job, so you do not have hundreds of thousands of signal integrity violations at the end."

Turning on the signal integrity mode will decrease the tool's performance, but Filseth said even with that feature running, it will still perform routing faster than v2.1, which did not have this ability.

With a router in place to complete the unified flow, Filseth said, users can take a design from the logic-generation phase and build a prototype up front that is silicon accurate. If necessary, they can then use "successive refinement" to complete their designs.

"When you build a first prototype with this flow, if that first prototype meets all your specifications, signal integrity and manufacturing goals, the design really takes off," said Filseth. "You have all the tools working together. It isn't like the traditional design where you start with a floorplan, go to routing, find a problem and then go back to floorplanning. In this flow there is no front-end and back-end - you do everything at once, what we call successive refinement."

Lower-cost subset

Along with the upgrade to SoC Encounter, Cadence is also introducing Nano Encounter, a lower-cost subset of the tool. According to Filseth, it is the same tool as SoC Encounter but does not have the hierarchy and chip-assemble capabilities built into it. The license fee for an annual subscription is $375,000, against SoC Encounter's $595,000.

In today's flows, design teams usually assign one or two engineers for every 1 million gates in a design, Filseth said. So, on a multimillion-gate design, users can have several licenses of Nano Encounter to route various blocks of the design and then use one license of SoC Encounter to tie those blocks together.

In Q4, Filseth said, Cadence plans to add its long-anticipated Open Access Database into the flow, tying in tools from third-party vendors.

SoC Encounter 2.2 and Nano Encounter run on Unix, but support for Linux is slated for availability by year's end.

- Michael Santarini

EE Times

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