Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Aldec: Taiwan to drive EDA development in Asia-Pacific region

Posted: 23 Sep 2002 ?? ?Print Version ?Bookmark and Share

Keywords:electronic design automation? eda software? soc design? asic design? kernel simulator?

Stanley Hyduke is President and CEO of Aldec Inc.
Taiwan continues to be Asia Pacific's no.1 consumer of EDA tools. As such, the demands of its marketplace help dictate the progression of technology as well as the maximum density that end-devices can bear.

Taiwan has evolved from primarily producing semiconductor devices to pioneering them, a major shift as many fab plants are relocating due to less expensive labor and various government incentives. The country is now taking a leading position in developing highly-advanced ASIC and SoC designs; designs that demand an efficient verification solution in order to meet development schedules.

The shift towards higher-end products makes it necessary for EDA software to be flexible enough to accommodate such densities, at the same time providing support for the entire design flow and any number of third-party tools that the system designer may be using.

As devices are becoming more dense and the average SoC design can take up to one year's time to develop, tools that are increasingly efficient are needed in order to help accelerate time to market on these designs that at times exceed 20 million gates.

System designers can save massive amounts of development time by using tools that help design development at all stages of the cycle. For example, many of the ASIC and SoC designs contain a mix of VHDL, Verilog and IP cores. Instead of verifying each component with a separate simulator, it is more efficient to use a simulator which concurrently verifies these components instead of adversely affecting verification time by using two discrete simulation kernels and the interface necessary for them to work together. Another advantage of a common kernel simulator is that the system designer is able to work from one comprehensive testbench instead of two incomplete and fragmented stimuli.

In addition to a common kernel simulator, design development is often dramatically accelerated with the introduction of hardware into the design cycle. A hardware board can offset up to 3 million ASIC gates, making software simulation much more efficient. A large percentage of Taiwan's system designers use IP cores and legacy designs in their designs, which can be easily accommodated in hardware with the use of a daughter board, saving the software environment for new design elements and the testbench of the entire design. Such hardware/software co-verification is becoming increasingly popular as it's no longer feasible to verify exclusively in a software environment.

With the migration from IC components to SoC designs, designs costs are continually increasing. For this matter, flexible tools that can accommodate cross-platforms (UNIX, Linux and Windows) are a cost-effective solution since the same tool can invariably be used on future designs, even if the O/S ultimately changes.

As device densities increase, requirements for efficient verification will only increase as well. Aldec Inc. is focused on providing ASIC and SoC solutions to decrease the verification times by delivering HDL simulation combined with System C support, hardware acceleration, and interfaces to high level testbench products developed by Verisity, Synopsys Vera and open source products from Cadence Testbuilder.

Aldec's primary goal is to provide verification technology that will increase productivity and decrease time-to market through the development of new and innovative verification methodologies that allow design re-use as well as the ability to utilize new high-level language abstractions through languages such as System C or SuperLog.

Taiwan continues plays a pivotal role in the development of the EDA industry and the advancements of end-user technologies. By accelerating design verification, system designs can allot more development time to the designs itself and ensure that the devices they're designing exceed end-users' objectives.

As Taiwan's system designers continue to develop dense chipsets, EDA companies will work with them in order to provide the optimal tool solution for those designs. Aldec is committed to supporting the evolving needs of its customer base and is committed to delivering the best in design verification and integration to its designers.

- Stanley Hyduke

CEO and President

Aldec Inc.

Article Comments - Aldec: Taiwan to drive EDA developme...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top