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Toshiba proposes double-junction MRAM structure

Posted: 24 Sep 2002 ?? ?Print Version ?Bookmark and Share

Keywords:toshiba? mram? magnetic society? cmos switches? mtj cell fabrication?

Toshiba Corp. has developed a magnetic random-access memory (MRAM) with a double-tunnel-junction structure - a key step, the company said, toward its goal of boosting MRAM density to the 1Gb level. The research team presented the results Wednesday (Sept. 18) at the 26th annual meeting of the Magnetic Society of Japan.

One of the major challenges to realizing large-density MRAM is raising the signal output (sense voltage) from each cell, claimed the company, which earlier this month entered into partnership with NEC Corp. to develop a 256Mb MRAM. Equally urgent, Toshiba engineers said, is establishing a finer process for magnetic-tunneling-junction (MTJ) cell fabrication.

By introducing a double-junction structure, Toshiba claimed it has solved both problems, and succeeded in doubling the signal output even when about 1V is applied.

Toshiba developed a test memory array by fabricating MTJ cells on CMOS switches in a 0.18?m process. "By introducing a double-tunnel-junction structure in the MTJ cell, we verified that the cell worked as a memory with a large signal output, about twice larger than thus far reported," said Hiroaki Yoda, laboratory leader at Toshiba's corporate research and development center.

An MTJ, or tunneling-magnetoresistive (TMR) element, has a multilayer structure of a very thin insulating layer (the tunnel barrier) sandwiched by magnetic layers. When both magnetic layers magnetize in the same direction, tunnel current flows through the barrier and magnetoresistance decreases. This is the "0" status. When the two layers are magnetized in opposite directions, tunnel current does not flow, resulting a high resistance - the "1" status.

When the voltage applied across the junction is small, the resistance difference (the magnetoresistance ratio) between the two statuses is large enough, at nearly 50 percent. But when the applied voltage goes above 0.4V, the MR ratio decreases nearly by half and signal output from the cell becomes low. "At present, the signal output barely satisfies the requirement for a 64Mb memory, but it is far short for a larger-density part," said Yoda.

Toshiba engineers built the double-tunnel barrier structure using undisclosed materials. While conventional single-junction TMR elements consist of three layers, Toshiba's double-junction TMR element has five. The magnetic layer that switches magnetized direction is at the center, sandwiched by tunnel barriers. They in turn are surrounded by layers with a fixed magnetized direction.

"It could be inferred that a larger signal would be produced from the double-tunnel-junction cells, because the applied voltage becomes half at each junction," said Yoshiaki Saito, senior research scientist at Toshiba's corporate R&D center. "But it was a challenge to form two very thin tunnel barriers precisely."

A 200mV signal output, or 100 mV, is considered the requirement for a 1Gb memory. Toshiba's test chip achieved a signal output of more than 90 mV.

"We believe that the double-tunnel junction is essential for TMR elements used for MRAM," Yoda said. By optimizing materials for the central magnetic layer, Toshiba engineers expect that the signal output can be further increased.

"Though the structure becomes less simple, the performance of the MTJ cell with double junctions seems to be improved in every aspect," said Saito.

- Yoshiko Hara

EE Times





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